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litex-boards
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Merge branch 'master' into axu2cga_software

This commit is contained in:
enjoy-digital 2022-02-15 08:21:29 +01:00 committed by GitHub
parent 5eca41ac73 6bbf8c8268
commit 896884dd21
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GPG Key ID: 4AEE18F83AFDEB23
96 changed files with 213 additions and 204 deletions
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4
litex_boards/platforms/alchitry_au.py
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@ -99,13 +99,13 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, variant="au"):
def __init__(self, variant="au", toolchain="vivado"):
device = {
"au": "xc7a35t-ftg256-1",
"au+": "xc7a100t-ftg256-2",
}[variant]
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
self.toolchain.bitstream_commands = [

4
litex_boards/platforms/alchitry_mojo.py
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@ -114,8 +114,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2-tqg144", _io)
def __init__(self, toolchain="ise"):
XilinxPlatform.__init__(self, "xc6slx9-2-tqg144", _io, toolchain=toolchain)
self.toolchain.additional_commands = ["write_bitstream -force -bin_file {build_name}"]
def do_finalize(self, fragment):

5
litex_boards/platforms/alinx_axu2cga.py
View File

@ -165,9 +165,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self):
XilinxPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain="vivado")
self.psu_config = psu_config
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain=toolchain)
def create_programmer(self, cable):
return OpenFPGALoader("axu2cga", cable)

4
litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py
View File

@ -124,8 +124,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, device="xc7k160tffg676-1"):
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
def __init__(self, device="xc7k160tffg676-1", toolchain="vivado"):
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/antmicro_lpddr4_test_board.py
View File

@ -98,8 +98,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, device="xc7k70tfbg484-1"):
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
def __init__(self, device="xc7k70tfbg484-1", toolchain="vivado"):
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/avalanche.py
View File

@ -99,8 +99,8 @@ class Platform(MicrosemiPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)
def __init__(self, toolchain="libero_soc_polarfire"):
MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io, toolchain=toolchain)
def do_finalize(self, fragment):
MicrosemiPlatform.do_finalize(self, fragment)

4
litex_boards/platforms/berkeleylab_marble.py
View File

@ -320,8 +320,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9 / 125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]

4
litex_boards/platforms/berkeleylab_marblemini.py
View File

@ -250,8 +250,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk20_vcxo"
default_clk_period = 1e9/20e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]

4
litex_boards/platforms/decklink_intensity_pro_4k.py
View File

@ -64,8 +64,8 @@ class Platform(XilinxPlatform):
default_clk_name = "debug" # FIXME.
default_clk_period = 1e9/100e6 # FIXME.
def __init__(self):
XilinxPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a70t.bit")

4
litex_boards/platforms/decklink_mini_4k.py
View File

@ -129,8 +129,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-fgg676-3", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-fgg676-3", _io, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/decklink_quad_hdmi_recorder.py
View File

@ -160,8 +160,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

3
litex_boards/platforms/digilent_arty.py
View File

@ -349,8 +349,7 @@ class Platform(XilinxPlatform):
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
if toolchain != "yosys+nextpnr": #this is not supported by yosys+pnr
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"

4
litex_boards/platforms/digilent_arty_s7.py
View File

@ -207,12 +207,12 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, variant="s7-50"):
def __init__(self, variant="s7-50", toolchain="vivado"):
device = {
"s7-25": "xc7s25csga324-1",
"s7-50": "xc7s50csga324-1"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

11
litex_boards/platforms/digilent_arty_z7.py
View File

@ -221,8 +221,8 @@ _connectors = [
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_freq = 125e6
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self, variant="z7-20", toolchain="vivado"):
device = {
@ -234,14 +234,11 @@ class Platform(XilinxPlatform):
"z7-20": "arty_z7_20"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors,
toolchain=toolchain)
self.default_clk_period = 1e9 / self.default_clk_freq
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader(self.board)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
self.default_clk_period)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e6/125e6)

14
litex_boards/platforms/digilent_atlys.py
View File

@ -219,8 +219,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self,):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
def __init__(self, toolchain="ise"):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors, toolchain=toolchain)
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def create_programmer(self):
@ -228,8 +228,8 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 0, loose=True), 1e9/74.25e6)
self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 1, loose=True), 1e9/74.25e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/25e6)
self.add_period_constraint(self.lookup_request("fx2:ifclk", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 0, loose=True), 1e9/74.25e6)
self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 1, loose=True), 1e9/74.25e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/25e6)
self.add_period_constraint(self.lookup_request("fx2:ifclk", loose=True), 1e9/100e6)

4
litex_boards/platforms/digilent_basys3.py
View File

@ -121,8 +121,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit")

4
litex_boards/platforms/digilent_cmod_a7.py
View File

@ -83,8 +83,8 @@ class Platform(XilinxPlatform):
def __init__(self, variant="a7-35", toolchain="vivado"):
device = {
"a7-35": "xc7a35tcpg236-1"
}[variant]
"a7-35": "xc7a35tcpg236-1"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
def create_programmer(self):

4
litex_boards/platforms/digilent_genesys2.py
View File

@ -157,8 +157,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):

4
litex_boards/platforms/digilent_nexys4.py
View File

@ -219,8 +219,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):

4
litex_boards/platforms/digilent_nexys4ddr.py
View File

@ -182,8 +182,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]")
def create_programmer(self):

4
litex_boards/platforms/digilent_pynq_z1.py
View File

@ -166,8 +166,8 @@ class Platform(XilinxPlatform):
default_clk_name = "sysclk"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain=toolchain)
self.add_extension(_ps7_io)
self.add_extension(_hdmi_rx_io)
self.add_extension(_hdmi_tx_io)

9
litex_boards/platforms/digilent_zedboard.py
View File

@ -201,14 +201,13 @@ _connectors = [
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
self.default_clk_freq = 1e9 / self.default_clk_period
def create_programmer(self):
return OpenOCD(config="board/digilent_zedboard.cfg")

4
litex_boards/platforms/digilent_zybo_z7.py
View File

@ -92,8 +92,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain=toolchain)
self.add_extension(_ps7_io)
self.add_extension(_usb_uart_pmod_io)

4
litex_boards/platforms/ebaz4205.py
View File

@ -66,8 +66,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk33_333"
default_clk_period = 1e9/33.333e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain=toolchain)
self.add_extension(_ps7_io)
def create_programmer(self):

4
litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py
View File

@ -106,8 +106,8 @@ class Platform(EfinixPlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/50e6
def __init__(self):
EfinixPlatform.__init__(self, "Ti60F225C3", _io, _connectors, iobank_info=iobank_info, toolchain="efinity")
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "Ti60F225C3", _io, _connectors, iobank_info=iobank_info, toolchain=toolchain)
def create_programmer(self):
return EfinixProgrammer()

4
litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py
View File

@ -155,8 +155,8 @@ class Platform(EfinixPlatform):
default_clk_name = "clk40"
default_clk_period = 1e9/40e6
def __init__(self):
EfinixPlatform.__init__(self, "T120F576I4", _io, _connectors, iobank_info=_bank_info, toolchain="efinity")
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "T120F576I4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain)
def create_programmer(self):
return EfinixProgrammer()

4
litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py
View File

@ -89,8 +89,8 @@ class Platform(EfinixPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
EfinixPlatform.__init__(self, "T20F256C4", _io, _connectors, iobank_info=_bank_info, toolchain="efinity")
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "T20F256C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain)
def create_programmer(self):
return EfinixProgrammer()

4
litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py
View File

@ -66,8 +66,8 @@ class Platform(EfinixPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
EfinixPlatform.__init__(self, "T20F169C4", _io, _connectors, iobank_info=_bank_info, toolchain="efinity")
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "T20F169C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain)
def create_programmer(self):
return EfinixProgrammer()

4
litex_boards/platforms/efinix_xyloni_dev_kit.py
View File

@ -73,8 +73,8 @@ class Platform(EfinixPlatform):
default_clk_name = "clk33"
default_clk_period = 1e9/33.333e6
def __init__(self):
EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain="efinity")
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader("xyloni_spi")

4
litex_boards/platforms/ego1.py
View File

@ -142,8 +142,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/enclustra_mercury_kx2.py
View File

@ -75,8 +75,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")

4
litex_boards/platforms/enclustra_mercury_xu5.py
View File

@ -88,8 +88,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/fairwaves_xtrx.py
View File

@ -111,8 +111,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk60"
default_clk_period = 1e9/60e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",

4
litex_boards/platforms/jungle_electronics_fireant.py
View File

@ -51,8 +51,8 @@ class Platform(EfinixPlatform):
default_clk_name = "clk33"
default_clk_period = 1e9/33.33e6
def __init__(self):
EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain="efinity")
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader("fireant")

4
litex_boards/platforms/kosagi_netv2.py
View File

@ -191,12 +191,12 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self, variant="a7-35"):
def __init__(self, variant="a7-35", toolchain="vivado"):
device = {
"a7-35": "xc7a35t-fgg484-2",
"a7-100": "xc7a100t-fgg484-2"
}[variant]
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"

4
litex_boards/platforms/krtkl_snickerdoodle.py
View File

@ -70,12 +70,12 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_freq = 100e6
def __init__(self, variant="z7-10"):
def __init__(self, variant="z7-10", toolchain="vivado"):
device = {
"z7-10": "xc7z010-clg400-1",
"z7-20": "xc7z020-clg400-3"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
self.default_clk_period = 1e9 / self.default_clk_freq
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"

5
litex_boards/platforms/lattice_ice40up5k_evn.py
View File

@ -116,9 +116,8 @@ class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors,
toolchain="icestorm")
def __init__(self, toolchain="icestorm"):
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain)
self.add_extension(serial)
self.add_extension(spiflash)

4
litex_boards/platforms/lattice_machxo3.py
View File

@ -44,8 +44,8 @@ class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io)
def __init__(self, toolchain="diamond"):
LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io, toolchain=toolchain)
def create_programmer(self):
_xcf_template = """

4
litex_boards/platforms/linsn_rv901t.py
View File

@ -291,8 +291,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors)
def __init__(self, toolchain="ise"):
XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx16.bit")

2
litex_boards/platforms/logicbone.py
View File

@ -197,7 +197,7 @@ class Platform(LatticePlatform):
self.revision = revision
io = {"rev0": _io_rev0 }[revision]
connectors = {"rev0": _connectors_rev0 }[revision]
LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain="trellis", **kwargs)
LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self):
return DFUProg(vid="1d50", pid="6130")

4
litex_boards/platforms/marble.py
View File

@ -320,8 +320,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9 / 125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]

4
litex_boards/platforms/marblemini.py
View File

@ -250,8 +250,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk20_vcxo"
default_clk_period = 1e9/20e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]

4
litex_boards/platforms/micronova_mercury2.py
View File

@ -54,8 +54,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35tftg256-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a35tftg256-1", _io, _connectors, toolchain=toolchain)
def do_finalize(self,fragment):
XilinxPlatform.do_finalize(self, fragment)

4
litex_boards/platforms/mist.py
View File

@ -81,8 +81,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk27"
default_clk_period = 1e9/27e6
def __init__(self):
AlteraPlatform.__init__(self, "EP3C25E144C8", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP3C25E144C8", _io, toolchain="quartus")
self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone III\"")
self.add_platform_command("set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144")
self.add_platform_command("set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED")

4
litex_boards/platforms/mnt_rkx7.py
View File

@ -115,8 +115,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")

4
litex_boards/platforms/myminieye_runber.py
View File

@ -103,8 +103,8 @@ class Platform(GowinPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-4")
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1N-4")
self.toolchain.options["use_mspi_as_gpio"] = 1
def create_programmer(self):

4
litex_boards/platforms/numato_aller.py
View File

@ -108,8 +108,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",

4
litex_boards/platforms/numato_mimas_a7.py
View File

@ -187,8 +187,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/numato_tagus.py
View File

@ -156,8 +156,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
self.toolchain.bitstream_commands = [

4
litex_boards/platforms/pano_logic_g2.py
View File

@ -132,10 +132,10 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self, revision="c"):
def __init__(self, revision="c", toolchain="ise"):
assert revision in ["b", "c"]
device = {"b": "xc6slx150-2-fgg484", "c": "xc6slx100-2-fgg484"}[revision]
XilinxPlatform.__init__(self, device, _io)
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
self.add_platform_command("""CONFIG VCCAUX="2.5";""")
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)

4
litex_boards/platforms/qmtech_10cl006.py
View File

@ -130,7 +130,7 @@ class Platform(AlteraPlatform):
),
]
def __init__(self, with_daughterboard=False):
def __init__(self, toolchain="quartus", with_daughterboard=False):
device = "10CL006YU256C8G"
io = _io
connectors = _connectors
@ -143,7 +143,7 @@ class Platform(AlteraPlatform):
else:
io += self.core_resources
AlteraPlatform.__init__(self, device, io, connectors)
AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
if with_daughterboard:
# an ethernet pin takes K22, so make it available

4
litex_boards/platforms/qmtech_5cefa2.py
View File

@ -129,7 +129,7 @@ class Platform(AlteraPlatform):
),
]
def __init__(self, with_daughterboard=False):
def __init__(self, toolchain="quartus", with_daughterboard=False):
device = "5CEFA2F23C8"
io = _io
connectors = _connectors
@ -142,7 +142,7 @@ class Platform(AlteraPlatform):
else:
io += self.core_resources
AlteraPlatform.__init__(self, device, io, connectors)
AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
if with_daughterboard:
# ethernet takes the config pin, so make it available

4
litex_boards/platforms/qmtech_ep4cex5.py
View File

@ -130,7 +130,7 @@ class Platform(AlteraPlatform):
),
]
def __init__(self, variant="ep4ce15", with_daughterboard=False):
def __init__(self, variant="ep4ce15", toolchain="quartus", with_daughterboard=False):
device = {
"ep4ce15": "EP4CE15F23C8",
"ep4ce55": "EP4CE55F23C8"
@ -146,7 +146,7 @@ class Platform(AlteraPlatform):
else:
io += self.core_resources
AlteraPlatform.__init__(self, device, io, connectors)
AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
if with_daughterboard:
# an ethernet pin takes K22, so make it available

4
litex_boards/platforms/qmtech_wukong.py
View File

@ -200,13 +200,13 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self, board_version=1, speed_grade=-2):
def __init__(self, board_version=1, speed_grade=-2, toolchain="vivado"):
io = _io_common
if board_version < 2:
io.extend(_io_v1)
else:
io.extend(_io_v2)
XilinxPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain="vivado")
XilinxPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/quicklogic_quickfeather.py
View File

@ -22,6 +22,6 @@ _io = [
# Platform -----------------------------------------------------------------------------------------
class Platform(QuickLogicPlatform):
def __init__(self):
QuickLogicPlatform.__init__(self, "ql-eos-s3", _io, toolchain="symbiflow")
def __init__(self, toolchain="symbiflow"):
QuickLogicPlatform.__init__(self, "ql-eos-s3", _io, toolchain=toolchain)

4
litex_boards/platforms/redpitaya.py
View File

@ -139,7 +139,7 @@ _connectors = [
class Platform(XilinxPlatform):
def __init__(self, board="redpitaya14"):
def __init__(self, board="redpitaya14", toolchain="vivado"):
if board == "redpitaya14":
device = "xc7z010clg400-1"
extension = _io_14
@ -153,7 +153,7 @@ class Platform(XilinxPlatform):
self.default_clk_period = 1e9/self.default_clk_freq
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
self.add_extension(extension)
self.add_extension(_ps7_io)
self.add_extension(_uart_io)

4
litex_boards/platforms/rz_easyfpga.py
View File

@ -53,8 +53,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE6E22C8", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP4CE6E22C8", _io, toolchain=toolchain)
def create_programmer(self):
return USBBlaster()

4
litex_boards/platforms/saanlima_pipistrello.py
View File

@ -157,8 +157,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
def __init__(self, toolchain="ise"):
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors, toolchain="ise")
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
def create_programmer(self):

4
litex_boards/platforms/scarabhardware_minispartan6.py
View File

@ -154,9 +154,9 @@ class Platform(XilinxPlatform):
default_clk_name = "clk32"
default_clk_period = 1e9/32e6
def __init__(self, device="xc6slx25"):
def __init__(self, device="xc6slx25", toolchain="ise"):
assert device in ["xc6slx9", "xc6slx25"]
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return XC3SProg(cable="ftdi")

4
litex_boards/platforms/seeedstudio_spartan_edge_accelerator.py
View File

@ -110,8 +110,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7s15-ftgb196", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7s15-ftgb196", _io, _connectors, toolchain=toolchain)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

4
litex_boards/platforms/siglent_sds1104xe.py
View File

@ -112,8 +112,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")

6
litex_boards/platforms/sipeed_tang_nano.py
View File

@ -47,9 +47,9 @@ class Platform(GowinPlatform):
default_clk_name = "clk24"
default_clk_period = 1e9/24e6
def __init__(self):
GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-1")
self.toolchain.options["use_done_as_gpio"] = 1
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1N-1")
self.toolchain.options["use_done_as_gpio"] = 1
self.toolchain.options["use_reconfign_as_gpio"] = 1
def create_programmer(self):

4
litex_boards/platforms/sipeed_tang_nano_4k.py
View File

@ -86,8 +86,8 @@ class Platform(GowinPlatform):
default_clk_name = "clk27"
default_clk_period = 1e9/27e6
def __init__(self):
GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain="gowin", devicename="GW1NSR-4C")
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain=toolchain, devicename="GW1NSR-4C")
self.toolchain.options["use_mode_as_gpio"] = 1
self.toolchain.options["use_mspi_as_gpio"] = 1
self.toolchain.options["use_done_as_gpio"] = 1

4
litex_boards/platforms/sipeed_tang_nano_9k.py
View File

@ -74,8 +74,8 @@ class Platform(GowinPlatform):
default_clk_name = "clk27"
default_clk_period = 1e9/27e6
def __init__(self):
GowinPlatform.__init__(self, "GW1NR-LV9QN88PC6/I5", _io, _connectors, toolchain="gowin", devicename="GW1NR-9C")
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1NR-LV9QN88PC6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9C")
self.toolchain.options["use_mspi_as_gpio"] = 1
def create_programmer(self):

4
litex_boards/platforms/sipeed_tang_primer.py
View File

@ -50,8 +50,8 @@ class Platform(AnlogicPlatform):
default_clk_name = "clk24"
default_clk_period = 1e9/24e6
def __init__(self):
AnlogicPlatform.__init__(self, "EG4S20BG256", _io, _connectors, toolchain="td")
def __init__(self, toolchain="td"):
AnlogicPlatform.__init__(self, "EG4S20BG256", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader("licheeTang")

4
litex_boards/platforms/sqrl_acorn.py
View File

@ -109,14 +109,14 @@ class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self, variant="cle-215+"):
def __init__(self, variant="cle-215+", toolchain="vivado"):
device = {
"cle-101": "xc7a100t-fgg484-2",
"cle-215": "xc7a200t-fbg484-2",
"cle-215+": "xc7a200t-fbg484-3"
}[variant]
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
self.add_extension(_serial_io)
self.add_extension(_sdcard_io)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")

4
litex_boards/platforms/sqrl_fk33.py
View File

@ -82,8 +82,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e-es1", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e-es1", _io, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/sqrl_xcu1525.py
View File

@ -269,8 +269,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk300"
default_clk_period = 1e9/300e6
def __init__(self):
XilinxPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/terasic_de0nano.py
View File

@ -132,8 +132,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io, _connectors)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return USBBlaster()

4
litex_boards/platforms/terasic_de10lite.py
View File

@ -122,8 +122,8 @@ class Platform(AlteraPlatform):
default_clk_period = 1e9/50e6
create_rbf = False
def __init__(self):
AlteraPlatform.__init__(self, "10M50DAF484C7G", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "10M50DAF484C7G", _io, toolchain=toolchain)
self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")

4
litex_boards/platforms/terasic_de10nano.py
View File

@ -166,8 +166,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io, toolchain=toolchain)
self.add_extension(_mister_sdram_module_io)
def create_programmer(self):

4
litex_boards/platforms/terasic_de1soc.py
View File

@ -130,8 +130,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io, _connectors)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return USBBlaster(cable_name="DE-SoC", device_id=2)

4
litex_boards/platforms/terasic_de2_115.py
View File

@ -46,8 +46,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE115F29C7", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP4CE115F29C7", _io, toolchain=toolchain)
def create_programmer(self):
return USBBlaster()

4
litex_boards/platforms/terasic_deca.py
View File

@ -292,8 +292,8 @@ class Platform(AlteraPlatform):
default_clk_period = 1e9/50e6
create_rbf = False
def __init__(self):
AlteraPlatform.__init__(self, "10M50DAF484C6GES", _io, _connectors)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "10M50DAF484C6GES", _io, _connectors, toolchain=toolchain)
# Disable config pin so bank8 can use 1.2V.
self.add_platform_command("set_global_assignment -name AUTO_RESTART_CONFIGURATION ON")
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")

4
litex_boards/platforms/terasic_sockit.py
View File

@ -186,10 +186,10 @@ class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self, revision="revd"):
def __init__(self, revision="revd", toolchain="quartus"):
assert revision in _device_map.keys()
self.revision = revision
AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard)
AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard, toolchain=toolchain)
def create_programmer(self):
return USBBlaster(cable_name="CV SoCKit")

4
litex_boards/platforms/trenz_c10lprefkit.py
View File

@ -126,8 +126,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
AlteraPlatform.__init__(self, "10CL055YU484A7G", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "10CL055YU484A7G", _io, toolchain=toolchain)
def create_programmer(self):
return USBBlaster(cable_name="Arrow-USB-Blaster")

4
litex_boards/platforms/trenz_cyc1000.py
View File

@ -67,8 +67,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
AlteraPlatform.__init__(self, "10CL025YU256C8G", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "10CL025YU256C8G", _io, toolchain=toolchain)
def create_programmer(self):
return USBBlaster(cable_name="Arrow-USB-Blaster")

4
litex_boards/platforms/trenz_max1000.py
View File

@ -86,8 +86,8 @@ class Platform(AlteraPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
AlteraPlatform.__init__(self, "10M08SAU169C8G", _io)
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "10M08SAU169C8G", _io, toolchain=toolchain)
self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")

4
litex_boards/platforms/trenz_te0725.py
View File

@ -78,8 +78,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35tcsg324-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a35tcsg324-2", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \

4
litex_boards/platforms/trenz_tec0117.py
View File

@ -108,8 +108,8 @@ class Platform(GowinPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, _connectors, toolchain="gowin", devicename='GW1NR-9')
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9")
def create_programmer(self):
return OpenFPGALoader("littleBee")

4
litex_boards/platforms/tul_pynq_z2.py
View File

@ -87,8 +87,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020clg400-1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z020clg400-1", _io, _connectors, toolchain=toolchain)
self.add_extension(_ps7_io)
self.add_extension(_usb_uart_pmod_io)

4
litex_boards/platforms/xilinx_ac701.py
View File

@ -234,8 +234,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")

4
litex_boards/platforms/xilinx_alveo_u250.py
View File

@ -332,8 +332,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk300"
default_clk_period = 1e9/300e6
def __init__(self):
XilinxPlatform.__init__(self, "xcu250-figd2104-2L-e", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcu250-figd2104-2L-e", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/xilinx_alveo_u280.py
View File

@ -224,8 +224,8 @@ class Platform(XilinxPlatform):
default_clk_name = "sysclk"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/xilinx_kc705.py
View File

@ -534,8 +534,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain)
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]

4
litex_boards/platforms/xilinx_kcu105.py
View File

@ -522,8 +522,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/xilinx_kv260.py
View File

@ -25,8 +25,8 @@ class Platform(XilinxPlatform):
default_clk_name = "pmod_hda16_cc"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
self.default_clk_freq = 1e9 / self.default_clk_period

4
litex_boards/platforms/xilinx_sp605.py
View File

@ -171,8 +171,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")
def __init__(self, toolchain="ise"):
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx45.bit")

4
litex_boards/platforms/xilinx_vc707.py
View File

@ -631,8 +631,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 1e9/156.25e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain=toolchain)
self.add_platform_command("""set_property CFGBVS VCCO [current_design]""")
self.add_platform_command("""set_property CONFIG_VOLTAGE 2.5 [current_design]""")

2
litex_boards/platforms/xilinx_vcu118.py
View File

@ -181,7 +181,7 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xcvu9p-flga2104-2-e", _io, _connectors, toolchain="vivado")
def create_programmer(self):

4
litex_boards/platforms/xilinx_zcu104.py
View File

@ -108,8 +108,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/xilinx_zcu106.py
View File

@ -95,8 +95,8 @@ class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain="vivado")
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()

4
litex_boards/platforms/ztex213.py
View File

@ -140,7 +140,7 @@ class Platform(XilinxPlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, variant="ztex2.13a", expansion="debug"):
def __init__(self, variant="ztex2.13a", toolchain="vivado", expansion="debug"):
device = {
"ztex2.13a": "xc7a35tcsg324-1",
#"ztex2.13b": "xc7a50tcsg324-1", #untested
@ -148,7 +148,7 @@ class Platform(XilinxPlatform):
#"ztex2.13c": "xc7a75tcsg324-2", #untested
#"ztex2.13d": "xc7a100tcsg324-2", #untested
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
if (expansion == "debug"):
self.add_extension(_debug_io)
else:

8
litex_boards/prog/openocd_litex_acorn_baseboard.cfg Normal file
View File

@ -0,0 +1,8 @@
adapter driver ftdi
adapter speed 2500
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0xfff8 0xfffb
reset_config none
source [find cpld/xilinx-xc7.cfg]
source [find fpga/lattice_ecp5.cfg]

8
litex_boards/targets/digilent_arty_z7.py
View File

@ -39,10 +39,14 @@ class _CRG(Module):
self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
else:
# Clk.
clk125 = platform.request("clk125")
# PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.register_clkin(clk125, 125e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)

8
litex_boards/targets/digilent_zedboard.py
View File

@ -37,10 +37,14 @@ class _CRG(Module):
self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
else:
# Clk.
clk100 = platform.request("clk100")
# PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)