Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms).

This commit is contained in:
Florent Kermarrec 2020-03-27 13:01:36 +01:00
parent cc2ac08ab9
commit 89dd00d3a2
1 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
litex_boards/platforms/aller.py
View File

@ -51,16 +51,6 @@ _io = [
), ),
# pcie # pcie
("pcie", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8 D11 B10 D9")),
Subsignal("rx_n", Pins("A8 C11 A10 C9")),
Subsignal("tx_p", Pins("B4 D5 B6 D7")),
Subsignal("tx_n", Pins("A4 C5 A6 C7"))
),
("pcie_x1", 0, ("pcie_x1", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")), Subsignal("clk_p", Pins("F6")),
@ -71,6 +61,16 @@ _io = [
Subsignal("tx_n", Pins("A4")) Subsignal("tx_n", Pins("A4"))
), ),
("pcie_x4", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8 D11 B10 D9")),
Subsignal("rx_n", Pins("A8 C11 A10 C9")),
Subsignal("tx_p", Pins("B4 D5 B6 D7")),
Subsignal("tx_n", Pins("A4 C5 A6 C7"))
),
# dram # dram
("ddram", 0, ("ddram", 0,
Subsignal("a", Pins( Subsignal("a", Pins(