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targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone

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This commit is contained in:
DerFetzer 2020-09-02 22:08:45 +02:00
parent cc78574297
commit 8bd736bd77
1 changed files with 5 additions and 4 deletions
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9
litex_boards/targets/colorlight_5a_75x.py
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@ -117,7 +117,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs): def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower() board = board.lower()
assert board in ["5a-75b", "5a-75e"] assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b": if board == "5a-75b":
@ -129,7 +129,7 @@ class BaseSoC(SoCCore):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset." assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, int(sys_clk_freq),
ident = "LiteX SoC on Colorlight " + board.upper(), ident = "LiteX SoC on Colorlight " + board.upper(),
ident_version = True, ident_version = True,
**kwargs) **kwargs)
@ -162,8 +162,8 @@ class BaseSoC(SoCCore):
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone: if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII( self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth")) pads = self.platform.request("eth", eth_phy))
self.add_csr("ethphy") self.add_csr("ethphy")
if with_ethernet: if with_ethernet:
self.add_ethernet(phy=self.ethphy) self.add_ethernet(phy=self.ethphy)
@ -193,6 +193,7 @@ def main():
soc = BaseSoC(board=args.board, revision=args.revision, soc = BaseSoC(board=args.board, revision=args.revision,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,
eth_phy = args.eth_phy,
sys_clk_freq = args.sys_clk_freq, sys_clk_freq = args.sys_clk_freq,
use_internal_osc = args.use_internal_osc, use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate, sdram_rate = args.sdram_rate,