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terasic_deca: fix cable name, ulpi, names, add gpio_serial

This commit is contained in:
Hans Baier 2021-03-26 09:38:26 +07:00
parent e2de69496a
commit 8c0ddd140b
2 changed files with 60 additions and 42 deletions
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34
litex_boards/platforms/terasic_deca.py
View File

@ -41,8 +41,8 @@ _io = [
# I2C: CapSense Buttons
("cap_sense_i2c", 0,
Subsignal("sclk", Pins("AB2")),
Subsignal("sdat", Pins("AB3")),
Subsignal("scl", Pins("AB2")),
Subsignal("sda", Pins("AB3")),
IOStandard("3.3-V LVTTL")
),
@ -55,7 +55,7 @@ _io = [
),
# power monitor I2C
("pmonitor", 0,
("pmonitor_i2c", 0,
Subsignal("alert", Pins("Y4")),
Subsignal("scl", Pins("Y3")),
Subsignal("sda", Pins("Y1")),
@ -63,7 +63,7 @@ _io = [
),
# temperature and humidity sensor I2C
("rh_temp", 0,
("rh_temp_i2c", 0,
Subsignal("drdy_n", Pins("AB9")),
Subsignal("scl", Pins("Y10")),
Subsignal("sda", Pins("AA10")),
@ -155,16 +155,16 @@ _io = [
IOStandard("1.5 V")
),
# USB ULPI
# USB ULPI TUSB1210
("ulpi", 0,
Subsignal("fault_n", Pins("D8"), IOStandard("1.2 V")),
Subsignal("clk", Pins("H11"), IOStandard("1.2 V")),
Subsignal("stp", Pins("J12")),
Subsignal("dir", Pins("J13")),
Subsignal("nxt", Pins("H12")),
Subsignal("reset_n", Pins("E16")),
Subsignal("data", Pins("E12 E13 H13 E14 H14 D15 E15 F15")),
IOStandard("1.8 V")
Subsignal("fault_n", Pins("D8"), IOStandard("1.2 V")),
Subsignal("cs", Pins("J11"), IOStandard("1.8 V")),
Subsignal("clk", Pins("H11"), IOStandard("1.2 V")),
Subsignal("stp", Pins("J12"), IOStandard("1.8 V")),
Subsignal("dir", Pins("J13"), IOStandard("1.8 V")),
Subsignal("nxt", Pins("H12"), IOStandard("1.8 V")),
Subsignal("reset_n", Pins("E16"), IOStandard("1.8 V")),
Subsignal("data", Pins("E12 E13 H13 E14 H14 D15 E15 F15"), IOStandard("1.8 V")),
),
("sdcard", 0,
@ -210,6 +210,7 @@ _io = [
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("1.8 V")
),
# HDMI_I2C
("hdmi_i2c", 0,
Subsignal("scl", Pins("C10")),
Subsignal("sda", Pins("B15")),
@ -263,6 +264,11 @@ _io = [
"P9:27 P9:28 P9:29 P9:30 P9:31 P9:41 P9:42"),
IOStandard("3.3-V LVTTL")
),
("gpio_serial", 0,
Subsignal("tx", Pins("P8:3")),
Subsignal("rx", Pins("P8:4")),
IOStandard("3.3-V LVTTL"))
]
# Connectors ---------------------------------------------------------------------------------------
@ -290,7 +296,7 @@ class Platform(AlteraPlatform):
self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
def create_programmer(self):
return USBBlaster()
return USBBlaster(cable_name="Arrow MAX 10 DECA")
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)

68
litex_boards/targets/terasic_deca.py
View File

@ -10,18 +10,14 @@ import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import deca
from litex.build.io import DDROutput
from litex_boards.platforms import deca
from litex.soc.cores.clock import Max10PLL
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoDVIPHY
from litex.soc.cores.led import LedChaser
from litex.soc.cores.clock import Max10PLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoDVIPHY
from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster
# CRG ----------------------------------------------------------------------------------------------
@ -30,24 +26,43 @@ class _CRG(Module):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_hdmi = ClockDomain()
self.clock_domains.cd_usb = ClockDomain()
# # #
# Clk / Rst
clk50 = platform.request("clk1_50")
# PLL
ulpi = platform.request("ulpi", 0)
clk1_50 = platform.request("clk1_50")
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.register_clkin(clk1_50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_hdmi, 40e6)
self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
self.comb += [
pll.reset.eq(self.rst),
ulpi.cs.eq(1) # enable ULPI chip, which enables the ULPI clock
]
pll.register_clkin(ulpi.clk, 60e6)
# the working example from the DECA kit uses -120 degrees for the USB core's
# and it works with the LUNA core too
pll.create_clkout(self.cd_usb, 60e6, phase=-120)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
platform = deca.Platform()
self.platform = platform = deca.Platform()
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Defaults to UART over JTAG because no hardware uart is on the board
if kwargs["uart_name"] == "serial":
@ -55,38 +70,35 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DECA",
ident_version = True,
ident = "LiteX SoC on Terasic DECA",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--debug", action="store_true", help="generate cpu debug interface")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
parser.add_argument("--integrated-ram-size", default=0x4000, help="Use FPGA block RAM as main RAM. Interim measure until we have DDR3 support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal,
integrated_main_ram_size = args.integrated_ram_size,
# use compressed instructions to save ROM
cpu_variant = "imac+debug" if args.debug else "imac",
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))