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targets/lattice_crossing: Avoid direct override of SoCCore.mem_map (break default SoCore.mem_map with updated imports).

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This commit is contained in:
Florent Kermarrec 2021-03-25 22:38:11 +01:00
parent b284fe47c3
commit e2de69496a
2 changed files with 2 additions and 2 deletions

2
litex_boards/targets/lattice_crosslink_nx_evn.py
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@ -63,7 +63,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
SoCCore.mem_map = {
mem_map = {
"rom": 0x00000000,
"sram": 0x40000000,
"csr": 0xf0000000,

2
litex_boards/targets/lattice_crosslink_nx_vip.py
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@ -64,7 +64,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
SoCCore.mem_map = {
mem_map = {
"rom": 0x00000000,
"sram": 0x40000000,
"csr": 0xf0000000,