terasic_deca: fix cable name, ulpi, names, add gpio_serial
This commit is contained in:
Hans Baier
parent
e2de69496a
commit
8c0ddd140b
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@ -41,8 +41,8 @@ _io = [
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# I2C: CapSense Buttons
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("cap_sense_i2c", 0,
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Subsignal("sclk", Pins("AB2")),
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Subsignal("sdat", Pins("AB3")),
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Subsignal("scl", Pins("AB2")),
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Subsignal("sda", Pins("AB3")),
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IOStandard("3.3-V LVTTL")
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),
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@ -55,7 +55,7 @@ _io = [
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),
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# power monitor I2C
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("pmonitor", 0,
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("pmonitor_i2c", 0,
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Subsignal("alert", Pins("Y4")),
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Subsignal("scl", Pins("Y3")),
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Subsignal("sda", Pins("Y1")),
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@ -63,7 +63,7 @@ _io = [
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),
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# temperature and humidity sensor I2C
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("rh_temp", 0,
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("rh_temp_i2c", 0,
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Subsignal("drdy_n", Pins("AB9")),
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Subsignal("scl", Pins("Y10")),
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Subsignal("sda", Pins("AA10")),
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@ -155,16 +155,16 @@ _io = [
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IOStandard("1.5 V")
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),
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# USB ULPI
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# USB ULPI TUSB1210
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("ulpi", 0,
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Subsignal("fault_n", Pins("D8"), IOStandard("1.2 V")),
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Subsignal("cs", Pins("J11"), IOStandard("1.8 V")),
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Subsignal("clk", Pins("H11"), IOStandard("1.2 V")),
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Subsignal("stp", Pins("J12")),
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Subsignal("dir", Pins("J13")),
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Subsignal("nxt", Pins("H12")),
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Subsignal("reset_n", Pins("E16")),
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Subsignal("data", Pins("E12 E13 H13 E14 H14 D15 E15 F15")),
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IOStandard("1.8 V")
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Subsignal("stp", Pins("J12"), IOStandard("1.8 V")),
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Subsignal("dir", Pins("J13"), IOStandard("1.8 V")),
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Subsignal("nxt", Pins("H12"), IOStandard("1.8 V")),
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Subsignal("reset_n", Pins("E16"), IOStandard("1.8 V")),
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Subsignal("data", Pins("E12 E13 H13 E14 H14 D15 E15 F15"), IOStandard("1.8 V")),
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),
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("sdcard", 0,
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@ -210,6 +210,7 @@ _io = [
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Misc("FAST_OUTPUT_REGISTER ON"),
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IOStandard("1.8 V")
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),
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# HDMI_I2C
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("hdmi_i2c", 0,
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Subsignal("scl", Pins("C10")),
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Subsignal("sda", Pins("B15")),
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@ -263,6 +264,11 @@ _io = [
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"P9:27 P9:28 P9:29 P9:30 P9:31 P9:41 P9:42"),
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IOStandard("3.3-V LVTTL")
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),
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("gpio_serial", 0,
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Subsignal("tx", Pins("P8:3")),
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Subsignal("rx", Pins("P8:4")),
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IOStandard("3.3-V LVTTL"))
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]
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# Connectors ---------------------------------------------------------------------------------------
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@ -290,7 +296,7 @@ class Platform(AlteraPlatform):
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self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
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def create_programmer(self):
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return USBBlaster()
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return USBBlaster(cable_name="Arrow MAX 10 DECA")
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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@ -10,18 +10,14 @@ import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import deca
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from litex.soc.cores.clock import Max10PLL
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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# CRG ----------------------------------------------------------------------------------------------
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@ -30,24 +26,43 @@ class _CRG(Module):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_usb = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk1_50")
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# PLL
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ulpi = platform.request("ulpi", 0)
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clk1_50 = platform.request("clk1_50")
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self.submodules.pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.register_clkin(clk1_50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 40e6)
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self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
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self.comb += [
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pll.reset.eq(self.rst),
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ulpi.cs.eq(1) # enable ULPI chip, which enables the ULPI clock
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]
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pll.register_clkin(ulpi.clk, 60e6)
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# the working example from the DECA kit uses -120 degrees for the USB core's
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# and it works with the LUNA core too
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pll.create_clkout(self.cd_usb, 60e6, phase=-120)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
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platform = deca.Platform()
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self.platform = platform = deca.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Defaults to UART over JTAG because no hardware uart is on the board
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if kwargs["uart_name"] == "serial":
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@ -55,31 +70,25 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on DECA",
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ident = "LiteX SoC on Terasic DECA",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--debug", action="store_true", help="generate cpu debug interface")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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parser.add_argument("--integrated-ram-size", default=0x4000, help="Use FPGA block RAM as main RAM. Interim measure until we have DDR3 support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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@ -87,6 +96,9 @@ def main():
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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integrated_main_ram_size = args.integrated_ram_size,
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# use compressed instructions to save ROM
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cpu_variant = "imac+debug" if args.debug else "imac",
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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