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targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).

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Florent Kermarrec 2021-03-11 09:48:26 +01:00
parent 0e2d9a571e
commit 8d3aaa8ea9
1 changed files with 2 additions and 0 deletions
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litex_boards/targets/nexys_video.py
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@ -37,6 +37,7 @@ class _CRG(Module):
self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi = ClockDomain()
self.clock_domains.cd_hdmi5x = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
# # # # # #
@ -52,6 +53,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_hdmi, 40e6) pll.create_clkout(self.cd_hdmi, 40e6)
pll.create_clkout(self.cd_hdmi5x, 5*40e6) pll.create_clkout(self.cd_hdmi5x, 5*40e6)
pll.create_clkout(self.cd_clk100, 100e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)