aliexpress_xc7k70t: Review/Cleanup.

- Cosmetic cleanups in platform.
- Add clk50 constraint.
- Remove JTAGBone specific support since now directly handled by LiteX.

README.md

@@ -97,6 +97,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
     ├── alchitry_cu
     ├── alchitry_mojo
     ├── aliexpress_xc7k420t
+    ├── aliexpress_xc7k70t
     ├── alinx_ax7010
     ├── alinx_axu2cga
     ├── analog_pocket

litex_boards/platforms/aliexpress_xc7k70t.py

@@ -103,14 +103,15 @@ _io = [
 
     # HDMI out
     ("hdmi_out", 0,
-        Subsignal("clk_p",   Pins("E10"), IOStandard("TMDS_33")),
+        Subsignal("clk_p",   Pins("E10")),
-        Subsignal("clk_n",   Pins("D10"), IOStandard("TMDS_33")),
+        Subsignal("clk_n",   Pins("D10")),
-        Subsignal("data0_p", Pins("D9"),  IOStandard("TMDS_33")),
+        Subsignal("data0_p", Pins("D9")),
-        Subsignal("data0_n", Pins("D8"),  IOStandard("TMDS_33")),
+        Subsignal("data0_n", Pins("D8")),
-        Subsignal("data1_p", Pins("C9"),  IOStandard("TMDS_33")),
+        Subsignal("data1_p", Pins("C9")),
-        Subsignal("data1_n", Pins("B9"),  IOStandard("TMDS_33")),
+        Subsignal("data1_n", Pins("B9")),
-        Subsignal("data2_p", Pins("A9"),  IOStandard("TMDS_33")),
+        Subsignal("data2_p", Pins("A9")),
-        Subsignal("data2_n", Pins("A8"),  IOStandard("TMDS_33")),
+        Subsignal("data2_n", Pins("A8")),
+        IOStandard("TMDS_33"),
     ),
 
     # PCIe
@@ -239,5 +240,6 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 
     def do_finalize(self, fragment):
         Xilinx7SeriesPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk50",         0, loose=True), 1e9/50e6)
         self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
         self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)

litex_boards/targets/aliexpress_xc7k70t.py

@@ -60,7 +60,6 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
         with_hdmi              = False,
         with_ethernet          = False,
-        with_jtagbone          = False,
         with_pcie              = False,
         with_sdram             = True,
         with_led_chaser        = True,
@@ -99,10 +98,6 @@ class BaseSoC(SoCCore):
             if with_video_framebuffer:
                 self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet:
             self.ethphy = LiteEthPHYRGMII(
@@ -134,7 +129,6 @@ def main():
     parser.add_target_argument("--sys-clk-freq",    default=90e6, type=float,  help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",      default="1:1",             help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
     parser.add_argument("--with-ethernet",          action="store_true",       help="Enable ethernet")
-    parser.add_argument("--with-jtagbone",  action="store_true", help="Enable JTAGbone")
     parser.add_argument("--with-pcie",              action="store_true",       help="Enable PCIe")
     parser.add_argument("--with-hdmi",              action="store_true",       help="Enable HDMI")
     viopts = parser.target_group.add_mutually_exclusive_group()
@@ -150,7 +144,6 @@ def main():
         sdram_rate             = args.sdram_rate,
         with_ethernet          = args.with_ethernet,
         with_pcie              = args.with_pcie,
-        with_jtagbone          = args.with_jtagbone,
         with_hdmi              = args.with_hdmi,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,