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aliexpress_xc7k70t: Review/Cleanup. 

- Cosmetic cleanups in platform.
- Add clk50 constraint.
- Remove JTAGBone specific support since now directly handled by LiteX.
This commit is contained in:
Florent Kermarrec 2023-11-09 08:26:06 +01:00
parent 8f43cfe18c
commit 8e3dc21ce5
3 changed files with 47 additions and 51 deletions
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1
README.md
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@ -97,6 +97,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── alchitry_cu ├── alchitry_cu
├── alchitry_mojo ├── alchitry_mojo
├── aliexpress_xc7k420t ├── aliexpress_xc7k420t
├── aliexpress_xc7k70t
├── alinx_ax7010 ├── alinx_ax7010
├── alinx_axu2cga ├── alinx_axu2cga
├── analog_pocket ├── analog_pocket

74
litex_boards/platforms/aliexpress_xc7k70t.py
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@ -42,15 +42,15 @@ _io = [
# SDRAM # SDRAM
("sdram_clock", 0, Pins("P23"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram_clock", 0, Pins("P23"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("sdram", 0, ("sdram", 0,
Subsignal("a", Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")), Subsignal("a", Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")),
Subsignal("dq", Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")), Subsignal("dq", Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")),
Subsignal("ba", Pins("K25 M24")), Subsignal("ba", Pins("K25 M24")),
Subsignal("dm", Pins("N23 G26")), Subsignal("dm", Pins("N23 G26")),
Subsignal("ras_n", Pins("N24")), Subsignal("ras_n", Pins("N24")),
Subsignal("cas_n", Pins("K26")), Subsignal("cas_n", Pins("K26")),
Subsignal("we_n", Pins("P26")), Subsignal("we_n", Pins("P26")),
Subsignal("cs_n", Pins("N26")), Subsignal("cs_n", Pins("N26")),
Subsignal("cke", Pins("J25")), Subsignal("cke", Pins("J25")),
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
Misc("SLEW = FAST") Misc("SLEW = FAST")
), ),
@ -103,14 +103,15 @@ _io = [
# HDMI out # HDMI out
("hdmi_out", 0, ("hdmi_out", 0,
Subsignal("clk_p", Pins("E10"), IOStandard("TMDS_33")), Subsignal("clk_p", Pins("E10")),
Subsignal("clk_n", Pins("D10"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("D10")),
Subsignal("data0_p", Pins("D9"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("D9")),
Subsignal("data0_n", Pins("D8"), IOStandard("TMDS_33")), Subsignal("data0_n", Pins("D8")),
Subsignal("data1_p", Pins("C9"), IOStandard("TMDS_33")), Subsignal("data1_p", Pins("C9")),
Subsignal("data1_n", Pins("B9"), IOStandard("TMDS_33")), Subsignal("data1_n", Pins("B9")),
Subsignal("data2_p", Pins("A9"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("A9")),
Subsignal("data2_n", Pins("A8"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("A8")),
IOStandard("TMDS_33"),
), ),
# PCIe # PCIe
@ -176,26 +177,26 @@ _connectors = [
# 3.3V # 3.3V
("HR_IO", { ("HR_IO", {
0 : "D19", 0 : "D19",
1 : "D18", 1 : "D18",
2 : "C21", 2 : "C21",
3 : "D20", 3 : "D20",
4 : "C22", 4 : "C22",
5 : "D21", 5 : "D21",
6 : "C24", 6 : "C24",
7 : "D23", 7 : "D23",
8 : "D24", 8 : "D24",
9 : "A19", 9 : "A19",
10 : "B19", 10 : "B19",
11 : "A20", 11 : "A20",
12 : "B20", 12 : "B20",
13 : "B21", 13 : "B21",
14 : "A23", 14 : "A23",
15 : "A24", 15 : "A24",
16 : "B25", 16 : "B25",
17 : "B26", 17 : "B26",
18 : "C26", 18 : "C26",
19 : "D25", 19 : "D25",
}), }),
# 3.3V # 3.3V
@ -231,7 +232,7 @@ set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
""") """)
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self): def create_programmer(self):
@ -239,5 +240,6 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
def do_finalize(self, fragment): def do_finalize(self, fragment):
Xilinx7SeriesPlatform.do_finalize(self, fragment) Xilinx7SeriesPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", 0, loose=True), 1e9/50e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)

23
litex_boards/targets/aliexpress_xc7k70t.py
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@ -60,7 +60,6 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1", def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
with_hdmi = False, with_hdmi = False,
with_ethernet = False, with_ethernet = False,
with_jtagbone = False,
with_pcie = False, with_pcie = False,
with_sdram = True, with_sdram = True,
with_led_chaser = True, with_led_chaser = True,
@ -99,10 +98,6 @@ class BaseSoC(SoCCore):
if with_video_framebuffer: if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi") self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet: if with_ethernet:
self.ethphy = LiteEthPHYRGMII( self.ethphy = LiteEthPHYRGMII(
@ -131,16 +126,15 @@ class BaseSoC(SoCCore):
def main(): def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=aliexpress_xc7k70t.Platform, description="LiteX SoC on AliExpress XC7K70T PCIe board.") parser = LiteXArgumentParser(platform=aliexpress_xc7k70t.Platform, description="LiteX SoC on AliExpress XC7K70T PCIe board.")
parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet") parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe") parser.add_argument("--with-hdmi", action="store_true", help="Enable HDMI")
parser.add_argument("--with-hdmi", action="store_true", help="Enable HDMI")
viopts = parser.target_group.add_mutually_exclusive_group() viopts = parser.target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).") viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
args = parser.parse_args() args = parser.parse_args()
# Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is # Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is
@ -150,7 +144,6 @@ def main():
sdram_rate = args.sdram_rate, sdram_rate = args.sdram_rate,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_pcie = args.with_pcie, with_pcie = args.with_pcie,
with_jtagbone = args.with_jtagbone,
with_hdmi = args.with_hdmi, with_hdmi = args.with_hdmi,
with_video_terminal = args.with_video_terminal, with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer, with_video_framebuffer = args.with_video_framebuffer,