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Merge pull request #116 from litex-hub/litedram_write_latency

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targets/s7/us: update sdram (manual cmd_latency no longer needed).
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enjoy-digital 2020-10-12 19:42:40 +02:00 committed by GitHub
commit 8e5b31646d
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10 changed files with 9 additions and 19 deletions
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1
litex_boards/targets/alveo_u250.py
View file

@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 1,
is_rdimm = True) is_rdimm = True)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",

3
litex_boards/targets/genesys2.py
View file

@ -63,8 +63,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/kc705.py
View file

@ -65,8 +65,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/kcu105.py
View file

@ -74,8 +74,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/kx2.py
View file

@ -62,8 +62,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/mercury_xu5.py
View file

@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/vc707.py
View file

@ -60,8 +60,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/vcu118.py
View file

@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/xcu1525.py
View file

@ -76,8 +76,7 @@ class BaseSoC(SoCCore):
pads = platform.request("ddram", ddram_channel), pads = platform.request("ddram", ddram_channel),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex_boards/targets/zcu104.py
View file

@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,