Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

targets/s7/us: update sdram (manual cmd_latency no longer needed).

Browse source
This commit is contained in:
Florent Kermarrec 2020-10-12 17:33:40 +02:00
parent ddf7038c78
commit c3ea04b6e9
10 changed files with 9 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
litex_boards/targets/alveo_u250.py
View file

@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1,
is_rdimm = True)
self.add_csr("ddrphy")
self.add_sdram("sdram",

3
litex_boards/targets/genesys2.py
View file

@ -63,8 +63,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/kc705.py
View file

@ -65,8 +65,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/kcu105.py
View file

@ -74,8 +74,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6,
cmd_latency = 1)
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/kx2.py
View file

@ -62,8 +62,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/mercury_xu5.py
View file

@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1)
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/vc707.py
View file

@ -60,8 +60,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/vcu118.py
View file

@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1)
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/xcu1525.py
View file

@ -76,8 +76,7 @@ class BaseSoC(SoCCore):
pads = platform.request("ddram", ddram_channel),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1)
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,

3
litex_boards/targets/zcu104.py
View file

@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
cmd_latency = 1)
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,