Merge pull request #589 from VOGL-electronic/sdram_efinix_trion_t20
efinix_trion_t20: add sdram
This commit is contained in:
commit
8eaa4d637e
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@ -49,6 +49,22 @@ _io = [
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Subsignal("miso", Pins("N1")),
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Subsignal("miso", Pins("N1")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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),
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# SDRAM NDS36PT5-20ET
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("sdram_clock", 0, Pins("P16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("C12 D11 C11 E11 J13 J14 J15 K12 K14 L15 D12 L16 M12")),
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Subsignal("dq", Pins("B14 A14 B13 A13 B12 B11 A11 B10 K15 E16 D16 C16 C15 B16 B15 A15")),
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Subsignal("ba", Pins("C14 C13")),
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Subsignal("dm", Pins("K16 B9")),
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Subsignal("ras_n", Pins("E12")),
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Subsignal("cas_n", Pins("H12")),
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Subsignal("we_n", Pins("J12")),
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Subsignal("cs_n", Pins("D13")),
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Subsignal("cke", Pins("M16")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS"),
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Misc("SLEW = FAST")
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),
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]
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]
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# Bank voltage ---------------------------------------------------------------------------------------
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# Bank voltage ---------------------------------------------------------------------------------------
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@ -15,6 +15,7 @@ from litex.gen import *
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from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit
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from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit
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from litex.build.io import ClkOutput
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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@ -22,12 +23,18 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litedram.modules import NDS36PT5
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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class _CRG(LiteXModule):
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name_sdram_clk = "sdram_clk"
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_sys_ps = ClockDomain()
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# # #
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# # #
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@ -39,6 +46,7 @@ class _CRG(LiteXModule):
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self.comb += pll.reset.eq(~rst_n | self.rst)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name=self.name_sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -52,6 +60,18 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", **kwargs)
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
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self.specials += ClkOutput(self.crg.name_sdram_clk, platform.request("sdram_clock"))
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self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = NDS36PT5(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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with_bist = kwargs.get("with_bist", False)
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)
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# SPI Flash --------------------------------------------------------------------------------
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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if with_spi_flash:
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from litespi.modules import W25Q32JV
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from litespi.modules import W25Q32JV
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@ -70,7 +90,7 @@ def main():
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from litex.build.parser import LiteXArgumentParser
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=efinix_trion_t20_bga256_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit.")
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parser = LiteXArgumentParser(platform=efinix_trion_t20_bga256_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sys-clk-freq", default=45e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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args = parser.parse_args()
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args = parser.parse_args()
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