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targets/digilent_netfpga_sume.py: Limit mapped SDRAM size as on other targets.

This commit is contained in:
Florent Kermarrec 2024-09-20 13:09:48 +02:00
parent 223367d6b6
commit 8f1350ec40
1 changed files with 3 additions and 2 deletions
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5
litex_boards/targets/digilent_netfpga_sume.py
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@ -74,11 +74,12 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq
)
)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8KTF51264(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------