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fix comment

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This commit is contained in:
Hans Baier 2023-05-16 03:03:30 +07:00
parent 45474f2e1b
commit 8f9d735630
1 changed files with 1 additions and 2 deletions
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litex_boards/platforms/pcbarts_klusterlab.py
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@ -75,8 +75,7 @@ _io = [
Subsignal("sys", Pins("C19")), Subsignal("sys", Pins("C19")),
IOStandard("LVCMOS33")), IOStandard("LVCMOS33")),
# The Serial which connects to the second UART # USB Serial
# of the FTDI on the base board (first FTDI port is JTAG)
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("A17")), Subsignal("tx", Pins("A17")),
Subsignal("rx", Pins("K15")), Subsignal("rx", Pins("K15")),