fix comment

2023-05-16 03:03:30 +07:00 · 2023-05-16 03:03:30 +07:00 · 8f9d735630
parent 45474f2e1b
commit 8f9d735630
1 changed files with 1 additions and 2 deletions
--- a/litex_boards/platforms/pcbarts_klusterlab.py
+++ b/litex_boards/platforms/pcbarts_klusterlab.py
@ -75,8 +75,7 @@ _io = [
        Subsignal("sys",  Pins("C19")),
        IOStandard("LVCMOS33")),

-    # The Serial which connects to the second UART
-    # of the FTDI on the base board (first FTDI port is JTAG)
+    # USB Serial
    ("serial", 0,
        Subsignal("tx",  Pins("A17")),
        Subsignal("rx",  Pins("K15")),