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partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices.

This commit is contained in:
Florent Kermarrec 2019-12-06 15:22:40 +01:00
parent 0a56d86b1a
commit 8fa3f09226
1 changed files with 10 additions and 5 deletions
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15
litex_boards/partner/targets/c10lprefkit.py
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@ -77,6 +77,8 @@ class _CRG(Module):
self.comb += self.cd_sys.clk.eq(clk_outs[0])
self.comb += self.cd_sys_ps.clk.eq(clk_outs[1])
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
platform.add_period_constraint(self.cd_sys.clk, 1e9/50e6)
platform.add_period_constraint(self.cd_sys_ps.clk, 1e9/50e6)
# BaseSoC ------------------------------------------------------------------------------------------
@ -133,14 +135,17 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").tx, 1e9/12.5e6)
self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").rx, 1e9/12.5e6)
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(
self.platform.lookup_request("clk12"),
self.platform.lookup_request("eth_clocks").tx,
self.platform.lookup_request("eth_clocks").rx
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk,
self.ethphy.crg.cd_eth_rx.clk
)
# Build --------------------------------------------------------------------------------------------
def main():