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targets/xilinx_zc706: temporary disabled ddr3

This commit is contained in:
Gwenhael Goavec-Merou 2024-03-29 07:11:06 +01:00
parent 2505aeb9b4
commit 917ae33351
1 changed files with 10 additions and 10 deletions
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20
litex_boards/targets/xilinx_zc706.py
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@ -89,16 +89,16 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
#if not self.integrated_main_ram_size:
# self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
# memtype = "DDR3",
# nphases = 4,
# sys_clk_freq = sys_clk_freq)
# self.add_sdram("sdram",
# phy = self.ddrphy,
# module = MT8JTF12864(sys_clk_freq, "1:4"),
# l2_cache_size = kwargs.get("l2_size", 8192)
# )
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone: