platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).

litex_boards/platforms/genesys2.py

@@ -134,7 +134,7 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
+        return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)

litex_boards/prog/openocd_genesys2.cfg

@@ -0,0 +1,14 @@
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_channel 1
+ftdi_layout_init 0x00e8 0x60eb
+reset_config none
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+adapter_khz 25000
+
+proc fpga_program {} {
+    global _CHIPNAME
+    xc7_program $_CHIPNAME.tap
+}