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platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).

This commit is contained in:
Florent Kermarrec 2020-06-23 11:55:50 +02:00
parent 55ed9fbf02
commit 936ba5b279
2 changed files with 15 additions and 1 deletions
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2
litex_boards/platforms/genesys2.py
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@ -134,7 +134,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def create_programmer(self): def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)

14
litex_boards/prog/openocd_genesys2.cfg Normal file
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@ -0,0 +1,14 @@
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 1
ftdi_layout_init 0x00e8 0x60eb
reset_config none
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
adapter_khz 25000
proc fpga_program {} {
global _CHIPNAME
xc7_program $_CHIPNAME.tap
}