Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.

This commit is contained in:
Florent Kermarrec 2020-03-09 09:29:09 +01:00
parent 3f191c8561
commit 95e1a05bf1
3 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex_boards/platforms/kcu105.py
View File

@ -498,6 +498,6 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 44]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 45]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 46]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")

12
litex_boards/platforms/vcu118.py
View File

@ -182,10 +182,10 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
# DDR4 memory channel C1 Internal Vref # DDR4 memory channel C1 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 71]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 72]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 73]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 73]")
# DDR4 memory channel C2 Internal Vref # DDR4 memory channel C2 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 40]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 41]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 42]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]")

4
litex_boards/platforms/zcu104.py
View File

@ -142,5 +142,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 65]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 66]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")