alinx_axau15/PCIe: Switch to Gen3/128-bit for now (configuration used on others Ultrascale+ Gen3 X4 boards).

2023-12-28 19:56:45 +01:00 · 2023-12-28 19:56:45 +01:00 · 982038508e
parent e229d1a0b6
commit 982038508e
1 changed files with 2 additions and 2 deletions
--- a/litex_boards/targets/alinx_axau15.py
+++ b/litex_boards/targets/alinx_axau15.py
@ -83,8 +83,8 @@ class BaseSoC(SoCCore):
        # PCIe -------------------------------------------------------------------------------------
        if with_pcie:
            self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
-                speed      = "gen4",
-                data_width = 256,
+                speed      = "gen3",
+                data_width = 128,
                bar0_size  = 0x20000)
            self.add_pcie(phy=self.pcie_phy, ndmas=1)