targets/icebreaker: simplify leds.
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@ -157,10 +157,9 @@ class BaseSoC(SoCCore):
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if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
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ledsignals = Signal(2)
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self.submodules.leds = GPIOOut(ledsignals)
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self.comb += platform.request("user_ledr_n").eq(ledsignals[0])
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self.comb += platform.request("user_ledg_n").eq(ledsignals[1])
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self.submodules.leds = GPIOOut(Cat(
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platform.request("user_ledr_n"),
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platform.request("user_ledg_n")))
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self.add_csr("leds")
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# self.add_memory_region("rom", 0x2001a000, 16 * 1024 * 1024 - 0x1a000, type="cached+linker")
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