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targets/c10lprefkit: fix default sys-clk-freq.

This commit is contained in:
Florent Kermarrec 2021-01-12 16:15:52 +01:00
parent 0a7443d273
commit 9ff90eb9fe
1 changed files with 1 additions and 1 deletions
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litex_boards/targets/c10lprefkit.py
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@ -109,7 +109,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=500e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)