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decklink_quad_hdmi_recorder: Increase sys_clk to 200MHz.

This commit is contained in:
Florent Kermarrec 2021-07-02 15:07:13 +02:00
parent b18f6a2c7f
commit a02855d105
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/decklink_quad_hdmi_recorder.py
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@ -58,7 +58,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, **kwargs):
platform = quad_hdmi_recorder.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -104,7 +104,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency (default: 200MHz)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
builder_args(parser)