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targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).

This commit is contained in:
Florent Kermarrec 2020-04-14 11:24:16 +02:00
parent 52c9648176
commit a12faae0fb
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/colorlight_5a_75b.py
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@ -64,7 +64,7 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6) pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
# SDRAM clock # SDRAM clock
@ -86,7 +86,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = M12L16161A(sys_clk_freq, "1:1"), module = M12L16161A(sys_clk_freq, "1:1"),