gsd_butterstick: Add optional SYZYGY GPIO (--with-syzygy-gpio) to expose the 32 GPIOs on SYZYGY breakout board.

This commit is contained in:
Florent Kermarrec 2022-01-06 18:37:42 +01:00
parent 144c0dc27e
commit a4130556ac
2 changed files with 27 additions and 13 deletions

View File

@ -175,6 +175,11 @@ _connectors_r1_0 = [
),
]
# SYZYGY -------------------------------------------------------------------------------------------
def raw_syzygy_io(syzygy, iostandard="LVCMOS33"):
return [(syzygy, 0, Pins(" ".join([f"{syzygy}:S{i:d}" for i in range(32)])), IOStandard(iostandard))]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):

View File

@ -27,6 +27,7 @@ from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.gpio import GPIOTristate
from litedram.modules import MT41K64M16,MT41K128M16,MT41K256M16,MT41K512M16
from litedram.phy import ECP5DDRPHY
@ -89,6 +90,7 @@ class BaseSoC(SoCCore):
eth_dynamic_ip = False,
with_spi_flash = False,
with_led_chaser = True,
with_syzygy_gpio = True,
**kwargs) :
platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain)
@ -147,6 +149,11 @@ class BaseSoC(SoCCore):
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_syzygy_gpio:
platform.add_extension(butterstick.raw_syzygy_io("SYZYGY0"))
self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0"))
# Build --------------------------------------------------------------------------------------------
def main():
@ -167,6 +174,7 @@ def main():
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
@ -185,6 +193,7 @@ def main():
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_spi_flash = args.with_spi_flash,
with_syzygy_gpio = args.with_syzygy_gpio,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()