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targets/lattice_crosslink_nx_evn: add main_ram section for firmware 

This takes the values from the Antmicro SDI MIPI converter as a model
and is enough to run a Zephyr hello world, but not seemingly enough for
a the Zephyr Shell sample.

Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13
This commit is contained in:
Josuah Demangeon 2023-08-18 19:00:28 +02:00
parent 3903cdee92
commit a5a6a313cc
1 changed files with 10 additions and 6 deletions
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10
litex_boards/targets/lattice_crosslink_nx_evn.py
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@ -64,8 +64,10 @@ class BaseSoC(SoCCore):
mem_map = { mem_map = {
"rom" : 0x00000000, "rom" : 0x00000000,
"sram" : 0x40000000, "sram" : 0x40000000,
"main_ram" : 0x60000000,
"csr" : 0xf0000000, "csr" : 0xf0000000,
} }
def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant", def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
with_led_chaser = True, with_led_chaser = True,
**kwargs): **kwargs):
@ -82,9 +84,11 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
# 128KB LRAM (used as SRAM) --------------------------------------------------------------- # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
size = 128*kB self.spram = NXLRAM(32, 64*kB)
self.spram = NXLRAM(32, size) self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
self.main_ram = NXLRAM(32, 64*kB)
self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser: