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Merge pull request #517 from bayi/master 

Digilent CMOD A7 ISSIRAM fix
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enjoy-digital 2023-08-08 19:29:32 +02:00 committed by GitHub
parent 9acc349893 4362cb23a1
commit 3903cdee92
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2 changed files with 4 additions and 1 deletions
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1
litex_boards/platforms/digilent_cmod_a7.py
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@ -49,6 +49,7 @@ _io = [
IOStandard("LVCMOS33")),
Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
Subsignal("oe", Pins("P19"), IOStandard("LVCMOS33")),
Misc("SLEW=FAST"),
),

4
litex_boards/targets/digilent_cmod_a7.py
View File

@ -56,6 +56,7 @@ class AsyncSRAM(LiteXModule):
data = issiram.data
wen = issiram.wen
cen = issiram.cen
oe = issiram.oe
########################
tristate_data = TSTriple(data_width)
self.specials += tristate_data.get_tristate(data)
@ -70,7 +71,8 @@ class AsyncSRAM(LiteXModule):
self.comb += [
cen.eq(~chip_ena),
wen.eq(~write_ena),
tristate_data.oe.eq(write_ena)
tristate_data.oe.eq(write_ena),
oe.eq(tristate_data.oe),
]
########################
# address and data