Fix Digilent Cmod A7 ISSIRAM reading

2023-08-05 19:56:32 +02:00 · 2023-08-05 19:56:32 +02:00 · 4362cb23a1
parent a6b025f7f3
commit 4362cb23a1
1 changed files with 1 additions and 0 deletions
--- a/litex_boards/targets/digilent_cmod_a7.py
+++ b/litex_boards/targets/digilent_cmod_a7.py
@ -56,6 +56,7 @@ class AsyncSRAM(LiteXModule):
        data = issiram.data
        wen = issiram.wen
        cen = issiram.cen
+        oe = issiram.oe
        ########################
        tristate_data = TSTriple(data_width)
        self.specials += tristate_data.get_tristate(data)