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Fix Digilent Cmod A7 ISSIRAM reading

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Bayi 2023-08-05 19:56:15 +02:00
parent efc15a91a9
commit a6b025f7f3
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2 changed files with 3 additions and 1 deletions
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1
litex_boards/platforms/digilent_cmod_a7.py
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@ -49,6 +49,7 @@ _io = [
IOStandard("LVCMOS33")),
Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
Subsignal("oe", Pins("P19"), IOStandard("LVCMOS33")),
Misc("SLEW=FAST"),
),

3
litex_boards/targets/digilent_cmod_a7.py
View File

@ -70,7 +70,8 @@ class AsyncSRAM(LiteXModule):
self.comb += [
cen.eq(~chip_ena),
wen.eq(~write_ena),
tristate_data.oe.eq(write_ena)
tristate_data.oe.eq(write_ena),
oe.eq(tristate_data.oe),
]
########################
# address and data