Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix Digilent Cmod A7 ISSIRAM reading

This commit is contained in:
Bayi 2023-08-05 19:56:15 +02:00
parent efc15a91a9
commit a6b025f7f3
No known key found for this signature in database
GPG Key ID: FC1B0679F450C368
2 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
litex_boards/platforms/digilent_cmod_a7.py
View File

@ -49,6 +49,7 @@ _io = [
IOStandard("LVCMOS33")), IOStandard("LVCMOS33")),
Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")), Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")), Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
Subsignal("oe", Pins("P19"), IOStandard("LVCMOS33")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
), ),

3
litex_boards/targets/digilent_cmod_a7.py
View File

@ -70,7 +70,8 @@ class AsyncSRAM(LiteXModule):
self.comb += [ self.comb += [
cen.eq(~chip_ena), cen.eq(~chip_ena),
wen.eq(~write_ena), wen.eq(~write_ena),
tristate_data.oe.eq(write_ena) tristate_data.oe.eq(write_ena),
oe.eq(tristate_data.oe),
] ]
######################## ########################
# address and data # address and data