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targets/xilinx_zc706: typo...

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Gwenhael Goavec-Merou 2024-03-29 07:18:19 +01:00
parent 27dce96bf8
commit a72f2a2e68
1 changed files with 1 additions and 1 deletions
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litex_boards/targets/xilinx_zc706.py
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@ -93,7 +93,7 @@ class BaseSoC(SoCCore):
# When nor jtagbone, nor etherbone are set forces jtagbone. # When nor jtagbone, nor etherbone are set forces jtagbone.
kwargs["uart_name"] = "crossover" kwargs["uart_name"] = "crossover"
if kwargs["with_jtagbone"] or with_etherbone: if not (kwargs["with_jtagbone"] or with_etherbone):
kwargs["with_jtagbone"] = True kwargs["with_jtagbone"] = True
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------