colorlight_5a_75b: add SoC with regular UART (on J19).
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@ -93,6 +93,13 @@ _io_v7_0 = [ # Documented by @miek
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# btn
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# btn
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("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")),
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("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")),
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# serial
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("serial", 0,
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Subsignal("tx", Pins("P11")), # led (J19 DATA_LED-)
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Subsignal("rx", Pins("M13")), # btn (J19 KEY+)
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IOStandard("LVCMOS33")
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),
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# spiflash (W25Q32JV)
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# spiflash (W25Q32JV)
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("spiflash", 0,
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("spiflash", 0,
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# clk
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# clk
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@ -3,17 +3,25 @@
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# License: BSD
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# Disclaimer: This SoC is still a Proof of Concept with large timings violations on the IP/UDP and
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# Build/Use ----------------------------------------------------------------------------------------
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# Etherbone stack that need to be optimized. It was initially just used to validate the reversed
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#
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# pinout but happens to work on hardware...
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# 1) SoC with regular UART and optional Ethernet connected to the CPU:
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# Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+.
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# Build/Use:
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# ./colorlight_5a_75b.py (add --with-ethernet to add Ethernet capability)
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# ./colorlight_5a_75b.py --load
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# You should see the LiteX BIOS and be able to interact with it.
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#
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# 2) SoC with UART in crossover mode over Etherbone:
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# ./colorlight_5a_75b.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv
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# ./colorlight_5a_75b.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv
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# ./colorlight_5a_75b.py --load
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# ./colorlight_5a_75b.py --load
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# ping 192.168.1.50
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# ping 192.168.1.50
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# Get and install wishbone tool from: https://github.com/litex-hub/wishbone-utils/releases
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# Get and install wishbone tool from: https://github.com/litex-hub/wishbone-utils/releases
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# wishbone-tool --ethernet-host 192.168.1.50 --server terminal --csr-csv csr.csv
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# wishbone-tool --ethernet-host 192.168.1.50 --server terminal --csr-csv csr.csv
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# You should see the LiteX BIOS and be able to interact with it.
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# You should see the LiteX BIOS and be able to interact with it.
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#
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# Disclaimer: SoC 2) is still a Proof of Concept with large timings violations on the IP/UDP and
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# Etherbone stack that need to be optimized. It was initially just used to validate the reversed
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# pinout but happens to work on hardware...
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import argparse
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import argparse
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import sys
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import sys
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@ -37,7 +45,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, with_rst=True):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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@ -45,7 +53,7 @@ class _CRG(Module):
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# Clk / Rst
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# Clk / Rst
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clk25 = platform.request("clk25")
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clk25 = platform.request("clk25")
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rst_n = platform.request("user_btn_n", 0)
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rst_n = 1 if not with_rst else platform.request("user_btn_n", 0)
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platform.add_period_constraint(clk25, 1e9/25e6)
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platform.add_period_constraint(clk25, 1e9/25e6)
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# PLL
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# PLL
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@ -64,13 +72,14 @@ class _CRG(Module):
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, revision, with_ethernet=False, with_etherbone=False, **kwargs):
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def __init__(self, revision, with_ethernet=False, with_etherbone=False, **kwargs):
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platform = colorlight_5a_75b.Platform(revision=revision)
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platform = colorlight_5a_75b.Platform(revision=revision)
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sys_clk_freq = int(125e6)
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sys_clk_freq = int(125e6) if with_etherbone else int(60e6)
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_rst=with_rst)
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# SDR SDRAM --------------------------------------------------------------------------------
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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if not self.integrated_main_ram_size:
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@ -101,11 +110,6 @@ class BaseSoC(SoCCore):
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self.add_csr("ethphy")
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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self.add_etherbone(phy=self.ethphy)
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# Led --------------------------------------------------------------------------------------
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led_counter = Signal(32)
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self.sync += led_counter.eq(led_counter + 1)
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self.comb += platform.request("user_led_n", 0).eq(led_counter[26])
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# Load ---------------------------------------------------------------------------------------------
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# Load ---------------------------------------------------------------------------------------------
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def load():
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def load():
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@ -122,7 +126,7 @@ adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
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""")
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""")
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f.close()
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f.close()
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os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
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os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
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exit()
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exit()
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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