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targets/netv2: add clk100 (for framebuffer)

This commit is contained in:
Florent Kermarrec 2019-09-11 23:02:21 +02:00
parent ec97d01feb
commit a92ce32f91
1 changed files with 2 additions and 0 deletions
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2
litex_boards/partner/targets/netv2.py
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@ -27,6 +27,7 @@ class _CRG(Module):
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain() self.clock_domains.cd_eth = ClockDomain()
# # # # # #
@ -41,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_eth, 50e6) pll.create_clkout(self.cd_eth, 50e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)