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plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints

This commit is contained in:
Gwenhael Goavec-Merou 2024-07-22 14:49:03 +02:00
parent 5d4ebeb09c
commit ab732011b3
3 changed files with 18 additions and 3 deletions
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7
litex_boards/platforms/lattice_certuspro_nx_evn.py
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@ -137,9 +137,14 @@ class Platform(LatticeNexusPlatform):
def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
assert device in ["LFCPNX"]
LatticeNexusPlatform.__init__(self, device + "-100-9LFG672C", _io, _connectors, toolchain=toolchain, **kwargs)
self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
# SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
# Evaluation mode (with free license)
self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
def create_programmer(self):
return OpenFPGALoader()
def do_finalize(self, fragment):
LatticeNexusPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)

7
litex_boards/platforms/lattice_certuspro_nx_versa.py
View File

@ -136,9 +136,14 @@ class Platform(LatticeNexusPlatform):
def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
assert device in ["LFCPNX"]
LatticeNexusPlatform.__init__(self, device + "-100-9LFG672I", _io, _connectors, toolchain=toolchain, **kwargs)
self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
# SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
# Evaluation mode (with free license)
self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
def create_programmer(self):
return OpenFPGALoader()
def do_finalize(self, fragment):
LatticeNexusPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clkin125", loose=True), 1e9/125e6)

7
litex_boards/platforms/lattice_certuspro_nx_vvml.py
View File

@ -110,9 +110,14 @@ class Platform(LatticeNexusPlatform):
def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
assert device in ["LFCPNX"]
LatticeNexusPlatform.__init__(self, device + "-100-9BBG484I", _io, _connectors, toolchain=toolchain, **kwargs)
self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
# SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
# Evaluation mode (with free license)
self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
def create_programmer(self):
return OpenFPGALoader()
def do_finalize(self, fragment):
LatticeNexusPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)