targets: import platforms from litex_boards.platforms

litex_boards/community/targets/ac701.py

@@ -8,7 +8,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.community.platforms import ac701
+from litex_boards.platforms import ac701
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import mem_decoder

litex_boards/community/targets/de10lite.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.community.platforms import de10lite
+from litex_boards.platforms import de10lite
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *

litex_boards/community/targets/de1soc.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.community.platforms import de1soc
+from litex_boards.platforms import de1soc
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *

litex_boards/community/targets/de2_115.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.community.platforms import de2_115
+from litex_boards.platforms import de2_115
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *

litex_boards/community/targets/ecp5_evn.py

@@ -8,7 +8,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.community.platforms import ecp5_evn
+from litex_boards.platforms import ecp5_evn
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *

litex_boards/official/targets/arty.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import arty
+from litex_boards.platforms import arty
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/de0nano.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import de0nano
+from litex_boards.platforms import de0nano
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *

litex_boards/official/targets/genesys2.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import genesys2
+from litex_boards.platforms import genesys2
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/kc705.py

@@ -9,7 +9,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import kc705
+from litex_boards.platforms import kc705
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/kcu105.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import kcu105
+from litex_boards.platforms import kcu105
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/minispartan6.py

@@ -11,7 +11,7 @@ from fractions import Fraction
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.official.platforms import minispartan6
+from litex_boards.platforms import minispartan6
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/nexys4ddr.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import nexys4ddr
+from litex_boards.platforms import nexys4ddr
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/nexys_video.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.official.platforms import nexys_video
+from litex_boards.platforms import nexys_video
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/official/targets/versa_ecp5.py

@@ -9,7 +9,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.official.platforms import versa_ecp5
+from litex_boards.platforms import versa_ecp5
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/partner/targets/netv2.py

@@ -7,7 +7,7 @@ import argparse
 
 from migen import *
 
-from litex_boards.partner.platforms import netv2
+from litex_boards.platforms import netv2
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/partner/targets/trellisboard.py

@@ -8,7 +8,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.partner.platforms import trellisboard
+from litex_boards.platforms import trellisboard
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *

litex_boards/partner/targets/ulx3s.py

@@ -9,7 +9,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.partner.platforms import ulx3s
+from litex_boards.platforms import ulx3s
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_sdram import *