targets/decklink_mini_4k: Update clock constraints.
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@ -46,7 +46,7 @@ class _CRG(LiteXModule):
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# Clk.
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clk100 = platform.request("clk100")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_s7pll0_clkin]")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets s7pll0_clkin]")
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# Main PLL.
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self.pll = pll = S7PLL(speedgrade=-1)
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