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orangecrab: defaults to USB-ACM UART.

This commit is contained in:
Florent Kermarrec 2021-01-08 19:00:58 +01:00
parent c6e75122d9
commit ae5494d7b6
1 changed files with 3 additions and 4 deletions
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7
litex_boards/targets/orangecrab.py
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@ -150,12 +150,11 @@ class BaseSoC(SoCCore):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# Serial ----------------------------------------------------------------------------------- # Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm": if kwargs["uart_name"] in ["serial", "usb_acm"]:
# FIXME: do proper install of ValentyUSB. kwargs["uart_name"] = "usb_acm"
# Defaults to USB ACM through ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb") sys.path.append("valentyusb")
else:
platform.add_extension(orangecrab.feather_serial)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,