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platform/stlv7325-v2: update VCCIO to fix --with-pcie generation

This commit is contained in:
Gabriel Somlo 2023-06-01 16:45:33 -04:00
parent 7fc8ca9816
commit b01abce7d5
1 changed files with 4 additions and 4 deletions
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8
litex_boards/platforms/sitlinv_stlv7325_v2.py
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@ -16,7 +16,7 @@ from litex.build.openocd import OpenOCD
def _get_io(voltage="2.5V"): def _get_io(voltage="2.5V"):
assert voltage in ["2.5V", "3.3V"] assert voltage in ["2.5V", "3.3V"]
VCCIO = str(25 if voltage == "2.5V" else 33) VCCIO = {"2.5V": "25", "3.3V": "33"}[voltage]
_io = [ _io = [
# Clk / Rst # Clk / Rst
("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")), ("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
@ -206,7 +206,7 @@ def _get_io(voltage="2.5V"):
# PCIe # PCIe
("pcie_x1", 0, ("pcie_x1", 0,
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("clk_p", Pins("H6")), Subsignal("clk_p", Pins("H6")),
Subsignal("clk_n", Pins("H5")), Subsignal("clk_n", Pins("H5")),
Subsignal("rx_p", Pins("B6")), Subsignal("rx_p", Pins("B6")),
@ -215,7 +215,7 @@ def _get_io(voltage="2.5V"):
Subsignal("tx_n", Pins("A3")) Subsignal("tx_n", Pins("A3"))
), ),
("pcie_x2", 0, ("pcie_x2", 0,
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("clk_p", Pins("H6")), Subsignal("clk_p", Pins("H6")),
Subsignal("clk_n", Pins("H5")), Subsignal("clk_n", Pins("H5")),
Subsignal("rx_p", Pins("B6 C4")), Subsignal("rx_p", Pins("B6 C4")),
@ -224,7 +224,7 @@ def _get_io(voltage="2.5V"):
Subsignal("tx_n", Pins("A3 B1")) Subsignal("tx_n", Pins("A3 B1"))
), ),
("pcie_x4", 0, ("pcie_x4", 0,
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("clk_p", Pins("H6")), Subsignal("clk_p", Pins("H6")),
Subsignal("clk_n", Pins("H5")), Subsignal("clk_n", Pins("H5")),
Subsignal("rx_p", Pins("B6 C4 E4 G4")), Subsignal("rx_p", Pins("B6 C4 E4 G4")),