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sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock 

As we do not need fine phase tweaking for the main system clock, use
S7PLL instead of S7MMCM to allow higher VCO frequency and more flexible
sys_clk_freq.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng 2022-11-16 23:25:49 +08:00
parent e11d40a249
commit b1107e94d4
1 changed files with 1 additions and 1 deletions
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2
litex_boards/targets/sitlinv_stlv7325.py
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@ -47,7 +47,7 @@ class _CRG(LiteXModule):
rst_n = platform.request("cpu_reset_n") rst_n = platform.request("cpu_reset_n")
# PLL. # PLL.
self.pll = pll = S7MMCM(speedgrade=-2) self.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(~rst_n | self.rst) self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk200, 200e6) pll.register_clkin(clk200, 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)