stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer.
This commit is contained in:
Florent Kermarrec
parent
174d958ca7
commit
b1550f006a
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@ -12,26 +12,22 @@ from litex.build.openocd import OpenOCD
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_io = [
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# Clk / Rst
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("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
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("clk200", 0,
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Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("AC11"), IOStandard("DIFF_SSTL15"))
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),
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# TODO verify / test (in docs)
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("clk156", 0,
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Subsignal("p", Pins("D6"), IOStandard("LVDS")),
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Subsignal("n", Pins("D5"), IOStandard("LVDS")),
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),
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# TODO verify / test (in docs)
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("clk150", 0,
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Subsignal("p", Pins("F6"), IOStandard("LVDS")),
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Subsignal("n", Pins("F5"), IOStandard("LVDS")),
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),
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("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
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("clk156", 0, # TODO verify / test (in docs)
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Subsignal("p", Pins("D6"), IOStandard("LVDS")),
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Subsignal("n", Pins("D5"), IOStandard("LVDS")),
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),
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("clk150", 0, # TODO verify / test (in docs)
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Subsignal("p", Pins("F6"), IOStandard("LVDS")),
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Subsignal("n", Pins("F5"), IOStandard("LVDS")),
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),
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# active low
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("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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# active low
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# Leds
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("user_led_n", 0, Pins("AA2"), IOStandard("LVCMOS15")),
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("user_led_n", 1, Pins("AD5"), IOStandard("LVCMOS15")),
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("user_led_n", 2, Pins("W10"), IOStandard("LVCMOS15")),
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@ -41,15 +37,16 @@ _io = [
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("user_led_n", 6, Pins("V11"), IOStandard("LVCMOS15")),
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("user_led_n", 7, Pins("Y12"), IOStandard("LVCMOS15")),
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# active low
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("user_key2_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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("user_key3_n", 0, Pins("C24"), IOStandard("LVCMOS33")), # J4 jumper 2.5V or 3.3V
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# Buttons
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("user_btn_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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("user_btn_n", 0, Pins("C24"), IOStandard("LVCMOS33")), # J4 jumper 2.5V or 3.3V
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# I2C
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("i2c", 0, # AT24C04
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# I2C / AT24C04
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("i2c", 0,
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Subsignal("scl", Pins("U19")),
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Subsignal("sda", Pins("U20")),
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IOStandard("LVCMOS25")),
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IOStandard("LVCMOS25")
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),
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# Serial
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("serial", 0,
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@ -60,16 +57,15 @@ _io = [
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AB7 AD11 AA8 AF10 AC7 AE11 AC8 AD8",
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"AC13 AF12 AF9 AD10 AE13 AF7 AB12"),
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Subsignal("a", Pins(
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"AB7 AD11 AA8 AF10 AC7 AE11 AC8 AD8",
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"AC13 AF12 AF9 AD10 AE13 AF7 AB12"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AE8 AA7 AF13"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AE7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AF8"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AA13"), IOStandard("SSTL15")), # 1R
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# Subsignal("cs_n", Pins("AD13"), IOStandard("SSTL15")), # 2R
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Subsignal("ba", Pins("AE8 AA7 AF13"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AE7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AF8"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AA13"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"AD16 AB16 AB19 V17 U1 AA3 AD6 AE1"),
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IOStandard("SSTL15")),
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@ -77,28 +73,30 @@ _io = [
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"AF17 AE17 AF15 AF14 AE15 AD15 AF20 AF19",
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"AA15 AA14 AC14 AD14 AB14 AB15 AA18 AA17",
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"AC18 AD18 AC17 AB17 AA20 AA19 AD19 AC19",
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"W14 V14 V19 V18 V16 W15 W16 Y17",
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"V4 U6 U5 U2 V3 W3 U7 V6",
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"Y3 Y2 V2 V1 W1 Y1 AB2 AC2",
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"AA4 AB4 AC4 AC3 AC6 AB6 Y6 Y5",
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"AD4 AD1 AF2 AE2 AE6 AE5 AF3 AE3"),
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" W14 V14 V19 V18 V16 W15 W16 Y17",
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" V4 U6 U5 U2 V3 W3 U7 V6",
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" Y3 Y2 V2 V1 W1 Y1 AB2 AC2",
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" AA4 AB4 AC4 AC3 AC6 AB6 Y6 Y5",
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" AD4 AD1 AF2 AE2 AE6 AE5 AF3 AE3"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AE18 Y15 AD20 W18 W6 AB1 AA5 AF5"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AF18 Y16 AE20 W19 W5 AC1 AB5 AF4"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")), # 1R
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Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")), # 1R
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# Subsignal("clk_p", Pins("AA10"), IOStandard("DIFF_SSTL15")), # 2R
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# Subsignal("clk_n", Pins("AB10"), IOStandard("DIFF_SSTL15")), # 2R
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Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")), # 1R
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# Subsignal("cke", Pins("AA9"), IOStandard("SSTL15")), # 2R
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Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")), # 1R
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# Subsignal("odt", Pins("Y13"), IOStandard("SSTL15")), # 2R
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Subsignal("reset_n", Pins("AB20"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")),
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#Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AB20"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=NORMAL")
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),
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# 2 Rank Signals:
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# Subsignal("cs_n", Pins("AD13"), IOStandard("SSTL15")),
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# Subsignal("clk_p", Pins("AA10"), IOStandard("DIFF_SSTL15")),
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# Subsignal("clk_n", Pins("AB10"), IOStandard("DIFF_SSTL15")),
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# Subsignal("cke", Pins("AA9"), IOStandard("SSTL15")),
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# Subsignal("odt", Pins("Y13"), IOStandard("SSTL15")),
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## TODO verify / test
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# # SPIFlash
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@ -303,7 +301,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a325t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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@ -22,7 +22,6 @@ from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import DDR3Module
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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@ -42,9 +41,14 @@ class _CRG(Module):
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# # #
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# Clk/Rst.
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clk200 = platform.request("clk200")
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rst_n = platform.request("cpu_reset_n")
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# PLL.
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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@ -72,12 +76,12 @@ class BaseSoC(SoCCore):
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq,
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT8JTF12864(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# Ethernet ---------------------------------------------------------------------------------
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