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stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer.

This commit is contained in:
Florent Kermarrec 2022-02-24 17:17:08 +01:00
parent 174d958ca7
commit b1550f006a
2 changed files with 53 additions and 51 deletions
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50
litex_boards/platforms/stlv7325.py
View File

@ -12,26 +12,22 @@ from litex.build.openocd import OpenOCD
_io = [
# Clk / Rst
("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
("clk200", 0,
Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("AC11"), IOStandard("DIFF_SSTL15"))
),
# TODO verify / test (in docs)
("clk156", 0,
("clk156", 0, # TODO verify / test (in docs)
Subsignal("p", Pins("D6"), IOStandard("LVDS")),
Subsignal("n", Pins("D5"), IOStandard("LVDS")),
),
# TODO verify / test (in docs)
("clk150", 0,
("clk150", 0, # TODO verify / test (in docs)
Subsignal("p", Pins("F6"), IOStandard("LVDS")),
Subsignal("n", Pins("F5"), IOStandard("LVDS")),
),
("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
# active low
("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
# active low
# Leds
("user_led_n", 0, Pins("AA2"), IOStandard("LVCMOS15")),
("user_led_n", 1, Pins("AD5"), IOStandard("LVCMOS15")),
("user_led_n", 2, Pins("W10"), IOStandard("LVCMOS15")),
@ -41,15 +37,16 @@ _io = [
("user_led_n", 6, Pins("V11"), IOStandard("LVCMOS15")),
("user_led_n", 7, Pins("Y12"), IOStandard("LVCMOS15")),
# active low
("user_key2_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
("user_key3_n", 0, Pins("C24"), IOStandard("LVCMOS33")), # J4 jumper 2.5V or 3.3V
# Buttons
("user_btn_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
("user_btn_n", 0, Pins("C24"), IOStandard("LVCMOS33")), # J4 jumper 2.5V or 3.3V
# I2C
("i2c", 0, # AT24C04
# I2C / AT24C04
("i2c", 0,
Subsignal("scl", Pins("U19")),
Subsignal("sda", Pins("U20")),
IOStandard("LVCMOS25")),
IOStandard("LVCMOS25")
),
# Serial
("serial", 0,
@ -68,8 +65,7 @@ _io = [
Subsignal("ras_n", Pins("Y7"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AE7"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AF8"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AA13"), IOStandard("SSTL15")), # 1R
# Subsignal("cs_n", Pins("AD13"), IOStandard("SSTL15")), # 2R
Subsignal("cs_n", Pins("AA13"), IOStandard("SSTL15")),
Subsignal("dm", Pins(
"AD16 AB16 AB19 V17 U1 AA3 AD6 AE1"),
IOStandard("SSTL15")),
@ -87,18 +83,20 @@ _io = [
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AF18 Y16 AE20 W19 W5 AC1 AB5 AF4"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")), # 1R
Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")), # 1R
# Subsignal("clk_p", Pins("AA10"), IOStandard("DIFF_SSTL15")), # 2R
# Subsignal("clk_n", Pins("AB10"), IOStandard("DIFF_SSTL15")), # 2R
Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")), # 1R
# Subsignal("cke", Pins("AA9"), IOStandard("SSTL15")), # 2R
Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")), # 1R
# Subsignal("odt", Pins("Y13"), IOStandard("SSTL15")), # 2R
Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")),
#Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AB20"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=NORMAL")
),
# 2 Rank Signals:
# Subsignal("cs_n", Pins("AD13"), IOStandard("SSTL15")),
# Subsignal("clk_p", Pins("AA10"), IOStandard("DIFF_SSTL15")),
# Subsignal("clk_n", Pins("AB10"), IOStandard("DIFF_SSTL15")),
# Subsignal("cke", Pins("AA9"), IOStandard("SSTL15")),
# Subsignal("odt", Pins("Y13"), IOStandard("SSTL15")),
## TODO verify / test
# # SPIFlash
@ -303,7 +301,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

16
litex_boards/targets/stlv7325.py
View File

@ -22,7 +22,6 @@ from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster
from litedram.modules import DDR3Module
from litedram.modules import MT8JTF12864
from litedram.phy import s7ddrphy
@ -42,9 +41,14 @@ class _CRG(Module):
# # #
# Clk/Rst.
clk200 = platform.request("clk200")
rst_n = platform.request("cpu_reset_n")
# PLL.
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
pll.register_clkin(platform.request("clk200"), 200e6)
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk200, 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
@ -72,12 +76,12 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
sys_clk_freq = sys_clk_freq,
)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------