targets/Ultrascale(+): Remove BUFGCE name overrides.

Not required, was only useful on a specific project.

litex_boards/targets/adi_adrv2crr_fmc.py

@@ -47,10 +47,10 @@ class CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/avnet_aesku40.py

@@ -45,10 +45,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -47,10 +47,10 @@ class _CRG(Module):
         pll.create_clkout(self.cd_idelay, 200e6)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
         self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)

litex_boards/targets/enclustra_mercury_xu5.py

@@ -39,10 +39,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/sqrl_xcu1525.py

@@ -44,10 +44,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/xilinx_alveo_u250.py

@@ -46,10 +46,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/xilinx_alveo_u280.py

@@ -72,10 +72,10 @@ class _CRG(Module):
             platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
             self.specials += [
-                Instance("BUFGCE_DIV", name="main_bufgce_div",
+                Instance("BUFGCE_DIV",
                     p_BUFGCE_DIVIDE=4,
                     i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-                Instance("BUFGCE", name="main_bufgce",
+                Instance("BUFGCE",
                     i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
                 # AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
             ]

litex_boards/targets/xilinx_kcu105.py

@@ -48,10 +48,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/xilinx_vcu118.py

@@ -40,10 +40,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/xilinx_zcu104.py

@@ -41,10 +41,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]
 

litex_boards/targets/xilinx_zcu106.py

@@ -45,10 +45,10 @@ class _CRG(Module):
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
-            Instance("BUFGCE", name="main_bufgce",
+            Instance("BUFGCE",
                 i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
         ]