Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash.

Tested with: ./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Nov 12 2021 08:37:48 BIOS CRC passed (2bec12a3) Migen git sha1: 7507a2b LiteX git sha1: f679992f --=============== SoC ==================-- CPU: VexRiscv @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128KiB SRAM: 8KiB FLASH: 4096KiB --========== Initialization ============-- Initializing W25Q32JV SPI Flash @0x00400000... Enabling Quad mode... First SPI Flash block erased, unable to perform freq test. Memspeed at 0x400000 (Sequential, 4.0KiB)... Read speed: 2.6MiB/s Memspeed at 0x400000 (Random, 4.0KiB)... Read speed: 1.5MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>
2025-01-03 03:43:36 -05:00 · 2021-11-12 08:42:10 +01:00 · 2021-11-12 08:42:10 +01:00 · b6c5a85b98
commit b6c5a85b98
parent d6fc4b412e
2 changed files with 153 additions and 0 deletions
--- a/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py
+++ b/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py
@ -0,0 +1,61 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.efinix.platform import EfinixPlatform
+from litex.build.efinix import EfinixProgrammer
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk
+    ("clk50", 0, Pins("D13"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
+
+    # Leds
+    ("user_led", 0, Pins("E1"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
+    ("user_led", 1, Pins("F2"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
+
+    # Buttons
+    ("user_btn", 0, Pins("F1"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
+    ("user_btn", 1, Pins("G2"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
+
+    # Serial
+    ("serial", 0,
+        Subsignal("tx", Pins("K5")), # J11:1
+        Subsignal("rx", Pins("K6")), # J11:2
+        IOStandard("3.3_V_LVTTL_/_LVCMOS"),
+        Misc("WEAK_PULLUP"),
+    ),
+
+    # SPIFlash
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("L1")),
+        Subsignal("clk",  Pins("K1")),
+        Subsignal("mosi", Pins("J1")),
+        Subsignal("miso", Pins("J2")),
+        IOStandard("3.3_V_LVTTL_/_LVCMOS")
+    ),
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = []
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(EfinixPlatform):
+    default_clk_name   = "clk50"
+    default_clk_period = 1e9/50e6
+
+    def __init__(self):
+        EfinixPlatform.__init__(self, "T20F169C4", _io, _connectors, toolchain="efinity")
+
+    def create_programmer(self):
+        return EfinixProgrammer()
+
+    def do_finalize(self, fragment):
+        EfinixPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
--- a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py
+++ b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py
@ -0,0 +1,92 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import efinix_trion_t20_mipi_dev_kit
+
+from litex.build.generic_platform import *
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.clock_domains.cd_sys = ClockDomain()
+
+        # # #
+
+        clk50 = platform.request("clk50")
+        rst_n = platform.request("user_btn", 0)
+
+        # PLL
+        self.submodules.pll = pll = TRIONPLL(platform)
+        self.comb += pll.reset.eq(~rst_n)
+        pll.register_clkin(clk50, 50e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
+        platform = efinix_trion_t20_mipi_dev_kit.Platform()
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident         = "LiteX SoC on Efinix Trion T20 MIPI Dev Kit",
+            ident_version = True,
+            **kwargs
+        )
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # SPI Flash --------------------------------------------------------------------------------
+        if with_spi_flash:
+            from litespi.modules import W25Q32JV
+            from litespi.opcodes import SpiNorFlashOpCodes as Codes
+            self.add_spi_flash(mode="1x", module=W25Q32JV(Codes.READ_1_1_1), with_master=True)
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T20 MIPI Dev Kit")
+    parser.add_argument("--build",          action="store_true", help="Build bitstream")
+    parser.add_argument("--load",           action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",   default=100e6,        help="System clock frequency (default: 100MHz)")
+    parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc     = BaseSoC(
+        sys_clk_freq   = int(float(args.sys_clk_freq)),
+        with_spi_flash = args.with_spi_flash,
+         **soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, f"{soc.build_name}.bit"))
+
+if __name__ == "__main__":
+    main()