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efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied).

This commit is contained in:
Florent Kermarrec 2021-11-12 07:58:51 +01:00
parent 7ce8567d9b
commit d6fc4b412e
2 changed files with 4 additions and 4 deletions
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4
litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
View File

@ -44,7 +44,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6),
def __init__(self, sys_clk_freq=int(100e6),
with_spi_flash = False,
with_ethernet = False,
with_etherbone = False,
@ -215,7 +215,7 @@ def main():
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")

4
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
View File

@ -42,7 +42,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
platform = efinix_trion_t20_bga256_dev_kit.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -74,7 +74,7 @@ def main():
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
builder_args(parser)
soc_core_args(parser)