alveo_u250: re-organize the auto-generated IOs, add build/load parameters.

litex_boards/platforms/alveo_u250.py

@@ -1,15 +1,17 @@
 # This file is Copyright (c) 2020 David Shah <dave@ds0.me>
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-# Note that this board file should also be applicable to
+# Note: This platform should also be applicable to the Alveo U200, VCU1525, BCU1525 and other
-# the Alveo U200, VCU1525, BCU1525 and other 1525 variants.
+# 1525 variants.
 
 from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
 
-# This part auto-generated by extract_xdc_pins.py
+# IOs (initially auto-generated by extract_xdc_pins.py) ---------------------------------------------
 
 _io = [
+    # clk / rst
     ("clk300", 0,
         Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
         Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
@@ -27,7 +29,36 @@ _io = [
         Subsignal("p", Pins("J16"), IOStandard("DIFF_SSTL12")),
     ),
     ("cpu_reset", 0, Pins("AL20"), IOStandard("LVCMOS12")),
-    ("ddr4_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
+
+    # led
+    ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
+    ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
+    ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
+
+    # switches
+    ("set_sw",  0, Pins("AL21")),
+    ("user_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")),
+    ("user_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")),
+    ("user_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")),
+    ("user_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")),
+
+    # gpio
+    ("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")),
+    ("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")),
+    ("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")),
+    ("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")),
+
+    ("serial", 0,
+        Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
+        Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
+    ),
+    ("serial_msp", 0,
+        Subsignal("rx", Pins("BA19"), IOStandard("LVCMOS12")),
+        Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")),
+    ),
+
+    # ddram
+    ("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
     ("ddram", 0,
         Subsignal("a", Pins(
             "AT36 AV36 AV37 AW35 AW36 AY36 AY35 BA40",
@@ -71,7 +102,7 @@ _io = [
         Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")),
         Misc("SLEW=FAST")
     ),
-    ("ddram_ch2", 0, 
+    ("ddram", 1,
         Subsignal("a", Pins(
             "AN24 AT24 AW24 AN26 AY22 AY23 AV24 BA22",
             "AY25 BA23 AM26 BA25 BB22 AL24"),
@@ -114,7 +145,7 @@ _io = [
         Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")),
         Misc("SLEW=FAST")
     ),
-    ("ddram_ch3", 0, 
+    ("ddram", 2,
         Subsignal("a", Pins(
             "L29 A33 C33 J29 H31 G31 C32 B32",
             "A32 D31 A34 E31 M30 F33"),
@@ -157,7 +188,7 @@ _io = [
         Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")),
         Misc("SLEW=FAST")
     ),
-    ("ddram_ch4", 0, 
+    ("ddram", 4,
         Subsignal("a", Pins(
             "K15 B15 F14 A15 C14 A14 B14 E13",
             "F13 A13 D14 C13 B13 K16"),
@@ -200,19 +231,19 @@ _io = [
         Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")),
         Misc("SLEW=FAST")
     ),
-    ("dip_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")),
+
-    ("dip_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")),
+    # i2c
-    ("dip_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")),
+    ("i2c_rst_n", 0, Pins("BF19"), IOStandard("LVCMOS12")),
-    ("dip_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")),
-    ("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")),
-    ("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")),
-    ("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")),
-    ("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")),
     ("i2c", 0,
         Subsignal("scl", Pins("BF20"), IOStandard("LVCMOS12")),
         Subsignal("sda", Pins("BF17"), IOStandard("LVCMOS12")),
     ),
-    ("i2c_main_reset_n", 0, Pins("BF19"), IOStandard("LVCMOS12")),
+
+    # si570
+    ("user_si570_clock", 0,
+        Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")),
+        Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")),
+    ),
     ("mgt_si570_clock", 0,
         Subsignal("n", Pins("M10")),
         Subsignal("p", Pins("M11")),
@@ -221,10 +252,12 @@ _io = [
         Subsignal("n", Pins("T10")),
         Subsignal("p", Pins("T11")),
     ),
+
+    # pcie
     ("pcie_x16", 0,
+        Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
         Subsignal("clk_n", Pins("AM10")),
         Subsignal("clk_p", Pins("AM11")),
-        Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
         Subsignal("rx_n", Pins(
             "AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3",
             "AP1 AR3 AT1 AU3 AV1 AW3 BA1 BC1")),
@@ -238,6 +271,8 @@ _io = [
             "AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9",
             "AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")),
     ),
+
+    # qsfp28
     ("qsfp28", 0,
         Subsignal("clk_n", Pins("K10")),
         Subsignal("clk_p", Pins("K11")),
@@ -270,22 +305,6 @@ _io = [
         Subsignal("txn", Pins("U8 T6 R8 P6")),
         Subsignal("txp", Pins("U9 T7 R9 P7")),
     ),
-    ("serial", 0, 
-        Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
-        Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
-    ),
-    ("serial_msp", 0, 
-        Subsignal("rx", Pins("BA19"), IOStandard("LVCMOS12")),
-        Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")),
-    ),
-    ("set_sw", 0, Pins("AL21")),
-    ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
-    ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
-    ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
-    ("user_si570_clock", 0, 
-        Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")),
-        Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")),
-    ),
 ]
 
 _connectors = []

litex_boards/targets/alveo_u250.py

@@ -17,6 +17,7 @@ from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
+from litex.soc.cores.led import LedChaser
 from litedram.modules import MTA18ASF2G72PZ
 from litedram.phy import usddrphy
 
@@ -32,7 +33,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(0)
+        self.comb += pll.reset.eq(0) # FIXME
         pll.register_clkin(platform.request("clk300", 0), 300e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
@@ -69,7 +70,6 @@ class BaseSoC(SoCCore):
                 cmd_latency      = 1,
                 is_rdimm         = True)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
@@ -80,20 +80,32 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
         self.add_ram("firmware_ram", 0x20000000, 0x8000)
 
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(3)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()