alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
This commit is contained in:
Florent Kermarrec
parent
c0b7afc739
commit
b9ee3a797a
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@ -1,15 +1,17 @@
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# This file is Copyright (c) 2020 David Shah <dave@ds0.me>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# Note that this board file should also be applicable to
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# the Alveo U200, VCU1525, BCU1525 and other 1525 variants.
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# Note: This platform should also be applicable to the Alveo U200, VCU1525, BCU1525 and other
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# 1525 variants.
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# This part auto-generated by extract_xdc_pins.py
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# IOs (initially auto-generated by extract_xdc_pins.py) ---------------------------------------------
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_io = [
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# clk / rst
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("clk300", 0,
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Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
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Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
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@ -27,7 +29,36 @@ _io = [
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Subsignal("p", Pins("J16"), IOStandard("DIFF_SSTL12")),
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),
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("cpu_reset", 0, Pins("AL20"), IOStandard("LVCMOS12")),
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("ddr4_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
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# led
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("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
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("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
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("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
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# switches
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("set_sw", 0, Pins("AL21")),
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("user_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")),
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("user_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")),
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("user_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")),
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("user_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")),
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# gpio
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("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")),
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("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")),
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("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")),
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("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")),
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("serial", 0,
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Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
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Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
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),
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("serial_msp", 0,
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Subsignal("rx", Pins("BA19"), IOStandard("LVCMOS12")),
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Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")),
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),
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# ddram
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("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
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("ddram", 0,
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Subsignal("a", Pins(
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"AT36 AV36 AV37 AW35 AW36 AY36 AY35 BA40",
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@ -71,7 +102,7 @@ _io = [
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Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")),
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Misc("SLEW=FAST")
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),
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("ddram_ch2", 0,
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("ddram", 1,
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Subsignal("a", Pins(
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"AN24 AT24 AW24 AN26 AY22 AY23 AV24 BA22",
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"AY25 BA23 AM26 BA25 BB22 AL24"),
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@ -114,7 +145,7 @@ _io = [
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Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")),
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Misc("SLEW=FAST")
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),
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("ddram_ch3", 0,
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("ddram", 2,
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Subsignal("a", Pins(
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"L29 A33 C33 J29 H31 G31 C32 B32",
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"A32 D31 A34 E31 M30 F33"),
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@ -157,7 +188,7 @@ _io = [
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Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")),
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Misc("SLEW=FAST")
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),
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("ddram_ch4", 0,
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("ddram", 4,
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Subsignal("a", Pins(
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"K15 B15 F14 A15 C14 A14 B14 E13",
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"F13 A13 D14 C13 B13 K16"),
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@ -200,19 +231,19 @@ _io = [
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Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")),
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Misc("SLEW=FAST")
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),
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("dip_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")),
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("dip_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")),
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("dip_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")),
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("dip_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")),
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("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")),
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("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")),
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("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")),
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("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")),
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# i2c
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("i2c_rst_n", 0, Pins("BF19"), IOStandard("LVCMOS12")),
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("i2c", 0,
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Subsignal("scl", Pins("BF20"), IOStandard("LVCMOS12")),
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Subsignal("sda", Pins("BF17"), IOStandard("LVCMOS12")),
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),
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("i2c_main_reset_n", 0, Pins("BF19"), IOStandard("LVCMOS12")),
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# si570
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("user_si570_clock", 0,
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Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")),
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Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")),
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),
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("mgt_si570_clock", 0,
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Subsignal("n", Pins("M10")),
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Subsignal("p", Pins("M11")),
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@ -221,10 +252,12 @@ _io = [
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Subsignal("n", Pins("T10")),
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Subsignal("p", Pins("T11")),
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),
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# pcie
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("pcie_x16", 0,
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Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
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Subsignal("clk_n", Pins("AM10")),
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Subsignal("clk_p", Pins("AM11")),
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Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
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Subsignal("rx_n", Pins(
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"AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3",
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"AP1 AR3 AT1 AU3 AV1 AW3 BA1 BC1")),
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@ -238,6 +271,8 @@ _io = [
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"AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9",
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"AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")),
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),
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# qsfp28
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("qsfp28", 0,
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Subsignal("clk_n", Pins("K10")),
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Subsignal("clk_p", Pins("K11")),
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@ -270,22 +305,6 @@ _io = [
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Subsignal("txn", Pins("U8 T6 R8 P6")),
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Subsignal("txp", Pins("U9 T7 R9 P7")),
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),
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("serial", 0,
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Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
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Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
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),
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("serial_msp", 0,
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Subsignal("rx", Pins("BA19"), IOStandard("LVCMOS12")),
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Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")),
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),
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("set_sw", 0, Pins("AL21")),
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("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
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("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
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("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
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("user_si570_clock", 0,
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Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")),
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Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")),
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),
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]
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_connectors = []
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@ -17,6 +17,7 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy import usddrphy
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@ -32,7 +33,7 @@ class _CRG(Module):
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(0)
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self.comb += pll.reset.eq(0) # FIXME
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pll.register_clkin(platform.request("clk300", 0), 300e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
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@ -69,7 +70,6 @@ class BaseSoC(SoCCore):
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cmd_latency = 1,
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is_rdimm = True)
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self.add_csr("ddrphy")
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self.add_constant("USDDRPHY_DEBUG")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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@ -80,20 +80,32 @@ class BaseSoC(SoCCore):
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l2_cache_reverse = True
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)
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# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
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self.add_ram("firmware_ram", 0x20000000, 0x8000)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(3)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
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if __name__ == "__main__":
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main()
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