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targets/add_sdram: Simplify call by removing useless arguments.

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- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
This commit is contained in:
Florent Kermarrec 2021-03-29 15:28:04 +02:00
parent 58286ce29e
commit ba01776432
51 changed files with 205 additions and 361 deletions
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11
litex_boards/targets/camlink_4k.py
View file

@ -92,13 +92,10 @@ class BaseSoC(SoCCore):
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"), module = MT41K64M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/colorlight_5a_75x.py
View file

@ -152,13 +152,10 @@ class BaseSoC(SoCCore):
sdram_cls = M12L16161A sdram_cls = M12L16161A
sdram_size = 0x40000000 sdram_size = 0x40000000
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate), module = sdram_cls(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", sdram_size), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/colorlight_i5.py
View file

@ -132,13 +132,10 @@ class BaseSoC(SoCCore):
# if board == "i5" and revision == "7.0": # if board == "i5" and revision == "7.0":
sdram_cls = M12L64322A # compat with EM638325-6H sdram_cls = M12L64322A # compat with EM638325-6H
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate), module = sdram_cls(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/digilent_arty.py
View file

@ -74,13 +74,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"), module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/digilent_arty_s7.py
View file

@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"), module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/digilent_genesys2.py
View file

@ -66,13 +66,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"), module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/digilent_nexys4ddr.py
View file

@ -73,13 +73,10 @@ class BaseSoC(SoCCore):
nphases = 2, nphases = 2,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT47H64M16(sys_clk_freq, "1:2"), module = MT47H64M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/digilent_nexys_video.py
View file

@ -79,13 +79,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K256M16(sys_clk_freq, "1:4"), module = MT41K256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/enclustra_mercury_kx2.py
View file

@ -65,13 +65,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = H5TC4G63CFR(sys_clk_freq, "1:4"), module = H5TC4G63CFR(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/enclustra_mercury_xu5.py
View file

@ -73,13 +73,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6) iodelay_clk_freq = 500e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT40A256M16(sys_clk_freq, "1:4"), module = MT40A256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/fpc_iii.py
View file

@ -106,13 +106,10 @@ class BaseSoC(SoCCore):
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits)) self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = IS43TR16256A(sys_clk_freq, "1:2"), module = IS43TR16256A(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x20000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1) self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1)

11
litex_boards/targets/gsd_orangecrab.py
View file

@ -191,13 +191,10 @@ class BaseSoC(SoCCore):
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"), module = sdram_module(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/hackaday_hadbadge.py
View file

@ -72,13 +72,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = AS4C32M8(sys_clk_freq, "1:1"), module = AS4C32M8(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

11
litex_boards/targets/kosagi_netv2.py
View file

@ -80,13 +80,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = K4B2G1646F(sys_clk_freq, "1:4"), module = K4B2G1646F(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/lambdaconcept_ecpix5.py
View file

@ -98,13 +98,10 @@ class BaseSoC(SoCCore):
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K256M16(sys_clk_freq, "1:2"), module = MT41K256M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

6
litex_boards/targets/lattice_crosslink_nx_evn.py
View file

@ -64,9 +64,9 @@ class _CRG(Module):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = { mem_map = {
"rom": 0x00000000, "rom" : 0x00000000,
"sram": 0x40000000, "sram" : 0x40000000,
"csr": 0xf0000000, "csr" : 0xf0000000,
} }
def __init__(self, sys_clk_freq=int(75e6), toolchain="radiant", **kwargs): def __init__(self, sys_clk_freq=int(75e6), toolchain="radiant", **kwargs):
platform = crosslink_nx_evn.Platform(toolchain=toolchain) platform = crosslink_nx_evn.Platform(toolchain=toolchain)

6
litex_boards/targets/lattice_crosslink_nx_vip.py
View file

@ -65,9 +65,9 @@ class _CRG(Module):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = { mem_map = {
"rom": 0x00000000, "rom": 0x00000000,
"sram": 0x40000000, "sram": 0x40000000,
"csr": 0xf0000000, "csr": 0xf0000000,
} }
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs): def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs):
platform = crosslink_nx_vip.Platform(toolchain=toolchain) platform = crosslink_nx_vip.Platform(toolchain=toolchain)

11
litex_boards/targets/lattice_versa_ecp5.py
View file

@ -102,13 +102,10 @@ class BaseSoC(SoCCore):
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"), module = MT41K64M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/linsn_rv901t.py
View file

@ -66,13 +66,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"), module = M12L64322A(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/logicbone.py
View file

@ -128,13 +128,10 @@ class BaseSoC(SoCCore):
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"), module = sdram_module(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/mist.py
View file

@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = MT48LC16M16(sys_clk_freq, "1:1"), module = MT48LC16M16(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x2000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Video Terminal --------------------------------------------------------------------------- # Video Terminal ---------------------------------------------------------------------------

11
litex_boards/targets/numato_aller.py
View file

@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"), module = MT41J128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------

11
litex_boards/targets/numato_mimas_a7.py
View file

@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"), module = MT41J128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/numato_nereid.py
View file

@ -73,13 +73,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------

11
litex_boards/targets/numato_tagus.py
View file

@ -77,13 +77,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"), module = MT41J128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------

11
litex_boards/targets/qmtech_ep4ce15.py
View file

@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(sys_clk_freq, sdram_rate), module = IS42S16160(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/qmtech_wukong.py
View file

@ -72,13 +72,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"), module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

12
litex_boards/targets/radiona_ulx3s.py
View file

@ -113,13 +113,11 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_reverse = False
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False
) )
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------

11
litex_boards/targets/saanlima_pipistrello.py
View file

@ -179,13 +179,10 @@ class BaseSoC(SoCCore):
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
] ]
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT46H32M16(sys_clk_freq, "1:2"), module = MT46H32M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

12
litex_boards/targets/scarabhardware_minispartan6.py
View file

@ -85,13 +85,11 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = AS4C16M16(sys_clk_freq, sdram_rate), module = AS4C16M16(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_reverse = False
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False
) )
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------

11
litex_boards/targets/siglent_sds1104xe.py
View file

@ -88,13 +88,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"), module = MT41K64M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------

11
litex_boards/targets/sqrl_acorn.py
View file

@ -92,13 +92,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"), module = MT41K512M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------

11
litex_boards/targets/sqrl_xcu1525.py
View file

@ -77,13 +77,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6) iodelay_clk_freq = 500e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT40A512M8(sys_clk_freq, "1:4"), module = MT40A512M8(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")

11
litex_boards/targets/terasic_de0nano.py
View file

@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(sys_clk_freq, sdram_rate), module = IS42S16160(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/terasic_de10lite.py
View file

@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16320(sys_clk_freq, "1:1"), module = IS42S16320(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Video Terminal --------------------------------------------------------------------------- # Video Terminal ---------------------------------------------------------------------------

11
litex_boards/targets/terasic_de10nano.py
View file

@ -81,13 +81,10 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = AS4C32M16(sys_clk_freq, sdram_rate), module = AS4C32M16(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Video Terminal --------------------------------------------------------------------------- # Video Terminal ---------------------------------------------------------------------------

11
litex_boards/targets/terasic_de1soc.py
View file

@ -65,13 +65,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16320(sys_clk_freq, "1:1"), module = IS42S16320(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

11
litex_boards/targets/terasic_de2_115.py
View file

@ -65,13 +65,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16320(self.clk_freq, "1:1"), module = IS42S16320(self.clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

34
litex_boards/targets/terasic_sockit.py
View file

@ -120,31 +120,15 @@ class BaseSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate) self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate)
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if mister_sdram == "xs_v22": sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = W9825G6KH6(sys_clk_freq, sdram_rate), module = sdrphy_mod(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192), )
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
if mister_sdram == "xs_v24":
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = AS4C32M16(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Video Terminal --------------------------------------------------------------------------- # Video Terminal ---------------------------------------------------------------------------
if with_video_terminal: if with_video_terminal:

11
litex_boards/targets/trellisboard.py
View file

@ -132,13 +132,10 @@ class BaseSoC(SoCCore):
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"), module = MT41J256M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/trenz_c10lprefkit.py
View file

@ -79,13 +79,10 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = MT48LC16M16(sys_clk_freq, "1:1"), module = MT48LC16M16(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

1
litex_boards/targets/trenz_tec0117.py
View file

@ -111,7 +111,6 @@ class BaseSoC(SoCCore):
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
origin = self.mem_map["main_ram"],
l2_cache_size = 128, l2_cache_size = 128,
l2_cache_min_data_width = 256, l2_cache_min_data_width = 256,
) )

11
litex_boards/targets/xilinx_ac701.py
View file

@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"), module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/xilinx_alveo_u250.py
View file

@ -78,13 +78,10 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
is_rdimm = True) is_rdimm = True)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------

11
litex_boards/targets/xilinx_alveo_u280.py
View file

@ -77,13 +77,10 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
is_rdimm = True) is_rdimm = True)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------

11
litex_boards/targets/xilinx_kc705.py
View file

@ -71,13 +71,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"), module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------

11
litex_boards/targets/xilinx_kcu105.py
View file

@ -80,13 +80,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"), module = EDY4016A(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------

11
litex_boards/targets/xilinx_vc707.py
View file

@ -67,13 +67,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"), module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------

11
litex_boards/targets/xilinx_vcu118.py
View file

@ -74,13 +74,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6) iodelay_clk_freq = 500e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"), module = EDY4016A(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/xilinx_zcu104.py
View file

@ -75,13 +75,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6) iodelay_clk_freq = 500e6)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), module = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

11
litex_boards/targets/ztex213.py
View file

@ -83,13 +83,10 @@ class BaseSoC(SoCCore):
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125 module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
origin = self.mem_map["main_ram"], size = 0x40000000,
size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192)
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
) )
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------