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trenz_tec0117: Use new DDROutput to generate SDRAM Clk.

This commit is contained in:
Florent Kermarrec 2021-07-14 10:02:58 +02:00
parent 94b985ac56
commit ba8321a3ab
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/trenz_tec0117.py
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@ -13,7 +13,7 @@ import importlib
from migen import * from migen import *
from litex.build.io import CRG from litex.build.io import DDROutput
from litex.soc.cores.clock.gowin_gw1n import GW1NPLL from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
self.dq = platform.request("IO_sdram_dq") self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads() sdram_pads = SDRAMPads()
self.comb += sdram_pads.clk.eq(~ClockSignal("sys")) # FIXME: use phase shift from PLL. self.specials += DDROutput(0, 1, sdram_pads.clk, ClockSignal("sys")) # FIXME: use phase shift from PLL.
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)