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decklink_quad_hdmi_recorder: Add pcie_lanes parameter and 4x/8x support.

This commit is contained in:
Florent Kermarrec 2022-03-23 15:19:40 +01:00
parent 73458ae9d7
commit bb974ae1af
1 changed files with 9 additions and 3 deletions
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12
litex_boards/targets/decklink_quad_hdmi_recorder.py
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@ -58,7 +58,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, **kwargs): def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, pcie_lanes=4, **kwargs):
platform = quad_hdmi_recorder.Platform() platform = quad_hdmi_recorder.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -87,10 +87,16 @@ class BaseSoC(SoCCore):
) )
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# FIXME: Does not seem to be working when also enabling DRAM. Has been tested succesfully by
# disabling DRAM with --integrated-main-ram-size=0x100.
if with_pcie: if with_pcie:
self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"), data_width = {
4 : 128,
8 : 256,
}[pcie_lanes]
self.submodules.pcie_phy = USPCIEPHY(platform, platform.request(f"pcie_x{pcie_lanes}"),
speed = "gen3", speed = "gen3",
data_width = 128, data_width = data_width,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1) self.add_pcie(phy=self.pcie_phy, ndmas=1)
# False Paths (FIXME: Improve integration). # False Paths (FIXME: Improve integration).